Memories: RAM, ROM Advanced TestbenchesSources & Required ReadingSlide 3Generic RAM (1)Generic RAM – inferring LUT-based RAM (2)Report from Synthesis (1)Report from Implementation (1)CLB SliceSlide 9Distributed RAMGeneric RAM – inferring Block RAM (2)Report from Synthesis (2)Report from Implementation (2)Single-Port Block RAMGeneric ROM (1)Generic ROM (2)Generic ROM (3) – hexadecimal notationSlide 18Slide 19RAM 16x1 (1)RAM 16x1 (2)RAM 16x1 (3)RAM 16x8 (1)RAM 16x8 (2)RAM 16x8 (3)ROM 16x1 (1)ROM 16x1 (2)ROM 16x1 (3)std_logic vs. std_ulogicConversion std_logic_vector => integer (1)Conversion std_logic_vector => integer (2)Instruction ROM example (1)Instruction ROM example (2)Generic dual-ported memory (1)Generic dual-ported memory (2)Report from ImplementationSlide 37Slide 38ConstantsConstants - featuresSlide 41Physical data typesTime values (physical literals) - ExamplesTIME valuesUnits of timeValues of the type TIMEArithmetic operations on values of the type TIMESlide 48Records – Examples (1)Records – Examples (2)Slide 51AssertAssert - syntaxAssert - ExamplesReport - syntaxReport - ExamplesSlide 57Variable – Example (1)Variable – Example (2)Variables - featuresSlide 61Slide 62Testbench (1)Testbench (2)Testbench (3)Testbench (4)Testbench (5)Slide 68Design Under Test (1)Design Under Test (2)Test vector file (1)Test vector file (2)Slide 73Slide 74Slide 75Slide 76Slide 77Slide 78Testbench (6)Testbench (7)Hex formatECE 545 – Introduction to VHDL George Mason UniversityMemories: RAM, ROMAdvanced TestbenchesECE 545Lecture 9ECE 545 – Introduction to VHDL 2Sources & Required Reading•Volnei A. Pedroni, Circuit Design with VHDLChapter 9.10, Memory DesignChapter 7.1, ConstantChapter 3.6, RecordsChapter 11.6, Assert•Sundar Rajan, Essential VHDL: RTL Synthesis Done RightChapter 14, starting from “Design Verification”ECE 545 – Introduction to VHDL 3GenericMemoriesECE 545 – Introduction to VHDL 4Generic RAM (1)LIBRARY ieee;USE ieee.std_logic_1164.all;-------------------------------------------------------------------------------------------------ENTITY ram ISGENERIC (bits: INTEGER:=8; -- # of bits per word words: INTEGER := 256); -- # of words in the memoryPORT (wr_ena, clk: IN STD_LOGIC; addr: IN INTEGER RANGE 0 to words-1; data_in: IN STD_LOGIC_VECTOR(bits -1 downto 0);data_out: OUT STD_LOGIC_VECTOR(bits - 1 downto 0) );END ram;ECE 545 – Introduction to VHDL 5Generic RAM – inferring LUT-based RAM (2)ARCHITECTURE LUT_based_ram OF ram ISTYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits-1 DOWNTO 0);SIGNAL memory: vector_array;BEGINPROCESS(clk)BEGINIF (rising_edge(clk)) THEN IF(wr_ena=‘1’) THEN memory(addr) <= data_in; END IF; END IF;END PROCESS;data_out <= memory(addr);END LUT_based_RAM;ECE 545 – Introduction to VHDL 6Report from Synthesis (1)Mapping to part: xc3s50vq100-5Cell usage:MUXF5 8 usesRAM64X1S 32 usesLUT3 20 usesRAM/ROM usage summarySingle Port Rams (RAM64X1S): 32Mapping Summary:Total LUTs: 148 (9%)ECE 545 – Introduction to VHDL 7Report from Implementation (1)Target Device : xc3s50Target Package : vq100Target Speed : -5Design Summary--------------Logic Utilization: Number of 4 input LUTs: 20 out of 1,536 1%Logic Distribution: Number of occupied Slices: 74 out of 768 9% Number of Slices containing only related logic: 74 out of 74 100% Number of Slices containing unrelated logic: 0 out of 74 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 148 out of 1,536 9% Number used as logic: 20 Number used for 32x1 RAMs: 128 (Two LUTs used per 32x1 RAM)ECE 545 – Introduction to VHDL 8COUTDQCKSRECDQCKRECOG4G3G2G1Look-UpTableCarry&ControlLogicOYBYF4F3F2F1XBXLook-UpTableF5INBYSRSCarry&ControlLogicCINCLKCESLICECLB SliceECE 545 – Introduction to VHDL 9The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)Xilinx Multipurpose LUTECE 545 – Introduction to VHDL 10RAM16X1SODWEWCLKA0A1A2A3RAM32X1SODWEWCLKA0A1A2A3A4RAM16X2SO1D0WEWCLKA0A1A2A3D1O0==LUTLUTorLUTRAM16X1DSPODWEWCLKA0A1A2A3DPRA0 DPODPRA1DPRA2DPRA3orDistributed RAM•CLB LUT configurable as Distributed RAM•A LUT equals 16x1 RAM•Implements Single and Dual-Ports•Cascade LUTs to increase RAM size•Synchronous write•Synchronous/Asynchronous read•Accompanying flip-flops used for synchronous readECE 545 – Introduction to VHDL 11Generic RAM – inferring Block RAM (2)ARCHITECTURE LUT_based_ram OF ram ISTYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits-1 DOWNTO 0);SIGNAL memory: vector_array;BEGINPROCESS(clk)BEGINIF (rising_edge(clk)) THEN IF(wr_ena=‘1’) THENmemory(addr) <= data_in; ELSEdata_out <= memory(addr); END IF; END IF;END PROCESS;END LUT_based_RAM;ECE 545 – Introduction to VHDL 12Report from Synthesis (2)Mapping to part: xc3s50pq208-5Cell usage:GND 1 useRAMB16_S9 1 useVCC 1 useRAM/ROM usage summaryBlock Rams : 1 of 4 (25%)Mapping Summary:Total LUTs: 0 (0%)ECE 545 – Introduction to VHDL 13Report from Implementation (2)Target Device : xc3s50Target Package : pq208Target Speed : -5Design Summary--------------Logic Utilization:Logic Distribution: Number of Slices containing only related logic: 0 out of 0 0% Number of Slices containing unrelated logic: 0 out of 0 0% *See NOTES below for an explanation of the effects of unrelated logic Number of bonded IOBs: 26 out of 124 20% Number of Block RAMs: 1 out of 4 25% Number of GCLKs: 1 out of 8 12%ECE 545 – Introduction to VHDL 14Single-Port Block RAMECE 545 – Introduction to VHDL 15Generic ROM (1)LIBRARY ieee;USE ieee.std_logic_1164.all;-------------------------------------------------------------------------------------------------ENTITY rom ISGENERIC (bits: INTEGER:=8; -- # of bits per word words: INTEGER := 8); -- # of words in the memoryPORT ( addr: IN INTEGER RANGE 0 TO words-1; data: OUT STD_LOGIC_VECTOR(bits – 1 DOWNTO 0) );END rom;ECE 545 – Introduction to VHDL 16Generic ROM (2)ARCHITECTURE behavioral OF rom ISTYPE