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MASON ECE 545 - Lecture 4 Behavioral & Structural Design Styles

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ECE 545 Lecture 4 Behavioral & Structural Design StylesResourcesSlide 3Anatomy of a ProcessStatement PartSlide 6What is a PROCESS?PROCESS with a SENSITIVITY LISTProcesses in VHDLSlide 10Component Equivalent of a ProcessSlide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Shift registerShift Register With Parallel LoadSlide 30Slide 31Slide 32Slide 33Slide 34Sequential Statements (1)Slide 36Slide 37Slide 38Slide 39Structural description – example (1)Structural description – example (2)Structural description – example (3)Slide 43Package – example (1)Package – example (2)Package usage (1)Package usage (2)Slide 48Configuration declarationConfiguration specification (1)Configuration specification (2)Slide 52Slide 53Example 1A 4-to-1 MultiplexerStraightforward code for Example 1Slide 57Modified code for Example 1Example 2A 2-to-4 binary decoderVHDL code for Example 2 (1)VHDL code for Example 2 (2)Iterative circuits: 8-bit comparator8-bit comparator: Truth TableSlide 65Basic building block – Truth Table8-bit comparator - ArchitectureArchitecture without for-generateSlide 69Slide 70Slide 71N-bit Comparator – Entity declarationN-bit Comparator – ArchitectureN-bit Comparator – InstantiationSlide 75Mixed Style ModelingECE 545 – Introduction to VHDL George Mason UniversityECE 545Lecture 4Behavioral & StructuralDesign StylesECE 545 – Introduction to VHDL 2Resources• Volnei A. Pedroni, Circuit Design with VHDLChapter 6, Sequential Code (sections 6.1-6.9)Chapter 10, Packages and Components• Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 4, Registers and Latches Chapter 9, Design PartitioningECE 545 – Introduction to VHDL 3Behavioral Design StyleECE 545 – Introduction to VHDL 4Anatomy of a Process[label:] process [(sensitivity list)] [declaration part]begin statement partend process [label];OPTIONALECE 545 – Introduction to VHDL 5Statement Part•Contains Sequential Statements to be Executed Each Time the Process Is Activated•Analogous to Conventional Programming LanguagesECE 545 – Introduction to VHDL 6Behavioral VHDL (subset)• sequential signal assignment ()• if-then-else statement•wait until•wait forMajor instructionsSelected sequential statementsECE 545 – Introduction to VHDL 7•A process can be given a unique name using an optional LABEL•This is followed by the keyword PROCESS•The keyword BEGIN is used to indicate the start of the process•All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important.•A process must end with the keywords END PROCESS.TESTING: process beginTEST_VECTOR<=“00”;wait for 10 ns;TEST_VECTOR<=“01”;wait for 10 ns;TEST_VECTOR<=“10”;wait for 10 ns;TEST_VECTOR<=“11”;wait for 10 ns;end process;•A process is a sequence of instructions referred to as sequential statements.What is a PROCESS?The Keyword PROCESSECE 545 – Introduction to VHDL 8PROCESS with a SENSITIVITY LIST•List of signals to which the process is sensitive.•Whenever there is an event on any of the signals in the sensitivity list, the process fires.•Every time the process fires, it will run in its entirety.•WAIT statements are NOT ALLOWED in a processes with SENSITIVITY LIST.label: process (sensitivity list) declaration part begin statement part end process;ECE 545 – Introduction to VHDL 9Processes in VHDL•Processes Describe Sequential Behavior•Processes in VHDL Are Very Powerful Statements•Allow to define an arbitrary behavior that may be difficult to represent by a real circuit•Not every process can be synthesized•Use Processes with Caution in the Code to Be Synthesized•Use Processes Freely in TestbenchesECE 545 – Introduction to VHDL 10Use of Processes in the Synthesizable CodeECE 545 – Introduction to VHDL 11Component Equivalent of a Process•All signals which appear on the left of signal assignment statement (<=) are outputs e.g. y, z•All signals which appear on the right of signal assignment statement (<=) or in logic expressions are inputs e.g. w, a, b, c•All signals which appear in the sensitivity list are inputs e.g. clk•Note that not all inputs need to be included in the sensitivity listpriority: PROCESS (clk)BEGINIF w(3) = '1' THENy <= "11" ;ELSIF w(2) = '1' THEN y <= "10" ;ELSIF w(1) = c THENy <= a and b;ELSEz <= "00" ;END IF ;END PROCESS ;wayzprioritybcclkECE 545 – Introduction to VHDL 12RegistersECE 545 – Introduction to VHDL 13Clock D 0 1 1 – 0 1 0 1 Truth table Graphical symbolt 1 t 2 t 3 t 4 TimeClock D Q Timing diagramQ(t+1)Q(t)D latchD Q ClockECE 545 – Introduction to VHDL 14Clk D   0 1 0 1 Truth table t 1 t 2 t 3 t 4 TimeClock D Q Timing diagramQ(t+1)Q(t)D flip-flopD Q Clock Graphical symbol0 – Q(t)1 –ECE 545 – Introduction to VHDL 15LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY latch IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END latch ;ARCHITECTURE Behavior OF latch IS BEGINPROCESS ( D, Clock ) BEGINIF Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior; D latchD Q ClockECE 545 – Introduction to VHDL 16LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ;ARCHITECTURE Behavior_1 OF flipflop IS BEGINPROCESS ( Clock ) BEGIN IF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior_1 ; D flip-flopD Q ClockECE 545 – Introduction to VHDL 17LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ;ARCHITECTURE Behavior_2 OF flipflop IS BEGINPROCESSBEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; Q <= D ; END PROCESS ; END Behavior_2 ; D flip-flopD Q ClockECE 545 – Introduction to VHDL 18LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ;ARCHITECTURE Behavior OF flipflop IS BEGINPROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= '0' ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ;END Behavior ; D flip-flop with asynchronous resetD Q Clock ResetnECE 545 – Introduction to VHDL 19LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ;ARCHITECTURE Behavior OF flipflop IS BEGINPROCESS BEGIN


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