Algorithmic State Machines Advanced TestbenchesSources & Required ReadingSlide 3Algorithmic State MachineElements used in ASM charts (1)Elements used in ASM charts (2)Elements used in ASM charts (3)Slide 8Slide 9Slide 10ASM Chart for Mealy FSM – Example 2Slide 12Slide 13Slide 14ASM Chart for Control Unit - Example 3Slide 16Pseudocode for the sort operationStructure of a Typical Digital SystemHardware Design with RTL VHDLDatapath Circuit for the sort operationControl Circuit – Part 1Slide 22Slide 23VHDL code (1) – Entity declarationPackage components (1)Package components (2)Slide 27VHDL code (2) – Datapath signal declarationsSlide 29VHDL code (3) – Control unit signal declarationsSlide 31VHDL code (4) - DatapathVHDL code (5) - DatapathSlide 34VHDL code (6) – Control Unit Part 1VHDL code (7) – Control Unit Part 1Slide 37VHDL code (8) – Control Unit Part 2VHDL code (9) – Control Unit Part 2VHDL code (10) – Control Unit Part 2Simulation results for the sort operation (1) Loading the registers and starting sortingSimulation results for the sort operation (2) Completing sorting and reading out registersAlternative datapath based on tri-state buffersSlide 44Slide 45Testbench (1)Testbench (2)Testbench (3)Testbench (4)Testbench (5)Slide 51Design Under Test (1)Design Under Test (2)Test vector file (1)Test vector file (2)Slide 56Slide 57Slide 58Slide 59Slide 60Testbench (6)Testbench (7)Hex formatECE 545 – Introduction to VHDL George Mason UniversityAlgorithmic State MachinesAdvanced TestbenchesECE 545Lecture 6ECE 545 – Introduction to VHDL 2Sources & Required Reading•Stephen Brown and Zvonko Vranesic,Fundamentals of Digital Logic with VHDL Design Chapter 8.10Algorithmic State Machine (ASM) ChartsChapter 10.2.6Sort Operation (handouts distributed in class)• Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 14, starting from “Design Verification”ECE 545 – Introduction to VHDL 3Algorithmic State Machine (ASM)ChartsECE 545 – Introduction to VHDL 4Algorithmic State MachineAlgorithmic State Machine – representation of a Finite State Machine suitable for FSMs with a larger number of inputs and outputs compared to FSMs expressed using state diagrams and state tables.ECE 545 – Introduction to VHDL 5Elements used in ASM charts (1)Output signalsor actions(Moore type)State nameCondition expression0 (False) 1 (True)Conditional outputs or actions (Mealy type) (a) State box (b) Decision box(c) Conditional output boxECE 545 – Introduction to VHDL 6Elements used in ASM charts (2)•State box – represents a state. Equivalent to a node in a state diagram or a row in a state table.Moore type outputs are listed inside of the box. It is customary to write only the name of the signal that has to be asserted in the given state, e.g., z instead of z=1. Also, it might be useful to write an action to be taken, e.g., Count = Count + 1, and only later translate it to asserting a control signal that causes a given action to take place.ECE 545 – Introduction to VHDL 7Elements used in ASM charts (3)•Decision box – indicates that a given condition is to be tested and the exit path is to be chosen accordinglyThe condition expression consists of one or more inputs to the FSM.•Conditional output box – denotes output signals that are of the Mealy type. The condition that determines whether such outputs are generated is specified in the decision box.ECE 545 – Introduction to VHDL 8Moore FSM – Example 1: State diagramC z 1 = Reset B z 0 = A z 0 = w 0 = w 1 = w 1 = w 0 = w 0 = w 1 =ECE 545 – Introduction to VHDL 9w w w 0 1 0 1 0 1 A B C z Reset w w w 0 1 0 1 0 1 A B C z Reset ASM Chart for Moore FSM – Example 1ECE 545 – Introduction to VHDL 10A w 0 = z 0 = w 1 = z 1 = B w 0 = z 0 = Reset w 1 = z 0 = Mealy FSM – Example 2: State diagramECE 545 – Introduction to VHDL 11ASM Chart for Mealy FSM – Example 2w w 0 1 0 1 A B Reset zECE 545 – Introduction to VHDL 12Control Unit Example: Arbiter (1)Arbiterresetr1r2r3g1g2g3clockECE 545 – Introduction to VHDL 13Idle000 1xx Reset gnt1 g 1 1 = x1x gnt2 g 2 1 = xx1 gnt3 g 3 1 = 0xx 1xx 01x x0x 001 xx0 Control Unit Example: Arbiter (2)ECE 545 – Introduction to VHDL 14Control Unit Example: Arbiter (3)r 1 r 2 r 1 r 2 r 3 IdleReset gnt1 g 1 1 = gnt2 g 2 1 = gnt3 g 3 1 = r 1 r 1 r 1 r 2 r 3 r 2 r 3 r 1 r 2 r 3 r 1 r 2 r 1 r 2 r 3 IdleReset gnt1 g 1 1 = gnt2 g 2 1 = gnt3 g 3 1 = r 1 r 1 r 1 r 2 r 3 r 2 r 3 r 1 r 2 r 3ECE 545 – Introduction to VHDL 15ASM Chart for Control Unit - Example 3r 1 r 3 0 1 1 IdleReset r 2 r 1 r 3 r 2 gnt1gnt2gnt31 1 1 0 0 0 g 1 g 2 g 3 0 0 1 r 1 r 3 0 1 1 IdleReset r 2 r 1 r 3 r 2 gnt1gnt2gnt31 1 1 0 0 0 g 1 g 2 g 3 0 0 1ECE 545 – Introduction to VHDL 16SortingECE 545 – Introduction to VHDL 17Pseudocode for the sort operationfor i = 0 tok 2 doA = R i ; for j = i + 1 tok 1 doB = R j ; ifB < A thenR i = B ; R j = A ; A = R i ; end if ; end for; end for; ––ECE 545 – Introduction to VHDL 18Structure of a Typical Digital SystemExecution Unit(Datapath)Control Unit(Control)Data InputsData OutputsControl InputsControl OutputsControl SignalsECE 545 – Introduction to VHDL 19Hardware Design with RTL VHDLPseudocodeExecution Unit Control UnitBlockdiagramBlockdiagramASMVHDL code VHDL code VHDL codeECE 545 – Introduction to VHDL 20Datapath Circuit for the sort operationE E E E Clock DataInWrInitRin3Rin2Rin1Rin0E E Bin AinDataOutRdABDataImuxBoutBltA1 0 A B 0 1 RDataR0R1R2R30 1 2 3 ABmuxn n n E E E E Clock DataInWrInitRin3Rin2Rin1Rin0E E Bin AinDataOutRdABDataImuxBoutBltA1 0 A B 0 1 RDataR0R1R2R30 1 2 3 ABmuxn n nECE 545 – Introduction to VHDL 21Control Circuit – Part 1L E L E 1 0 1 0 k 2 –= k –1 = LJEJLIEI2-to-4 decoderWrInitWrRAddClock CselIntImux2 C i C j z i z j CmuxRin0 Rin1 Rin2 Rin3 0 2 2 2 2 2 Counter Counter R Q Q R w 0 w 1 Eny 0 y 1 y 2 y 3 2 L E L E 1 0 1 0 k 2 –= k –1 = LJEJLIEI2-to-4 decoderWrInitWrRAddClock CselIntImux2 C i C j z i z j CmuxRin0 Rin1 Rin2 Rin3 0 2 2 2 2 2 Counter Counter R Q Q R w 0 w 1 Eny 0 y 1 y 2 y 3 2ECE 545 – Introduction to VHDL 22B A < ? C i 0 s 0 1 S1S2Dones Reset A R i  C j C i , C i C i 1 + S4S50 1 S3C j C j 1 + B R j R j A R i B A R i C j k 1 –= ? C j …