Behavioral Modeling of Sequential-Circuit Building BlocksRequired readingSlide 3VHDL Design StylesProcesses in VHDLAnatomy of a ProcessPROCESS with a SENSITIVITY LISTComponent Equivalent of a ProcessSlide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Asychronous vs. SynchronousSlide 19Slide 20A word on genericsSlide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Shift registerShift Register With Parallel LoadSlide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Circuit built of medium scale componentsStructural description – example (1)Structural description – example (2) VHDL-87Structural description – example (3) VHDL-87Structural description – example (4) VHDL-87Structural description – example (5) VHDL-87Structural description – example (2) VHDL-93Slide 46Slide 47Instruction ROM example (1)Instruction ROM example (2)Slide 50Slide 51Mixed Style ModelingSlide 53For BeginnersSlide 55For IntermmediatesFor Intermmediates (2)Slide 58DelaysInitializationsDual-edge triggered register/counter (1)Dual-edge triggered register/counter (2)Dual-edge triggered register/counter (3)George Mason UniversityBehavioral Modeling ofSequential-Circuit Building BlocksECE 545Lecture 62Required reading• P. Chu, RTL Hardware Design using VHDLChapter 5.1, VHDL ProcessChapter 8, Sequential Circuit Design: Principle3ECE 448 – FPGA and ASIC Design with VHDLBehavioral Design Style:Registers & Counters4VHDL Design StylesComponents andinterconnectsstructuralVHDL Design StylesdataflowConcurrent statementsbehavioral• Registers• Shift registers• Counters• State machinesSequential statementsand moreif you are carefulsynthesizable5Processes in VHDL•Processes Describe Sequential Behavior•Processes in VHDL Are Very Powerful Statements•Allow to define an arbitrary behavior that may be difficult to represent by a real circuit•Not every process can be synthesized•Use Processes with Caution in the Code to Be Synthesized•Use Processes Freely in Testbenches6Anatomy of a Process[label:] PROCESS [(sensitivity list)] [declaration part]BEGIN statement partEND PROCESS [label];OPTIONAL7PROCESS with a SENSITIVITY LIST•List of signals to which the process is sensitive.•Whenever there is an event on any of the signals in the sensitivity list, the process fires.•Every time the process fires, it will run in its entirety.•WAIT statements are NOT ALLOWED in a processes with SENSITIVITY LIST.label: process (sensitivity list) declaration part begin statement part end process;8Component Equivalent of a Process•All signals which appear on the left of signal assignment statement (<=) are outputs e.g. y, z•All signals which appear on the right of signal assignment statement (<=) or in logic expressions are inputs e.g. w, a, b, c•All signals which appear in the sensitivity list are inputs e.g. clk•Note that not all inputs need to be included in the sensitivity listpriority: PROCESS (clk)BEGINIF w(3) = '1' THENy <= "11" ;ELSIF w(2) = '1' THEN y <= "10" ;ELSIF w(1) = c THENy <= a and b;ELSEz <= "00" ;END IF ;END PROCESS ;wayzprioritybcclk9ECE 448 – FPGA and ASIC Design with VHDLRegisters10Clock D 0 1 1 – 0 1 0 1 Truth table Graphical symbolt 1 t 2 t 3 t 4 TimeClock D Q Timing diagramQ(t+1)Q(t)D latchD Q Clock11Clk D   0 1 0 1 Truth table t 1 t 2 t 3 t 4 TimeClock D Q Timing diagramQ(t+1)Q(t)D flip-flopD Q Clock Graphical symbol0 – Q(t)1 –12LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY latch IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END latch ;ARCHITECTURE behavioral OF latch IS BEGINPROCESS ( D, Clock ) BEGINIF Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END behavioral; D latchD Q Clock13LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ;ARCHITECTURE behavioral OF flipflop IS BEGINPROCESS ( Clock ) BEGIN IF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END behavioral ; D flip-flopD Q Clock14LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ;ARCHITECTURE behavioral2 OF flipflop IS BEGINPROCESS ( Clock ) BEGIN IF rising_edge(Clock) THEN Q <= D ; END IF ; END PROCESS ; END behavioral2; D flip-flopD Q Clock15LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ;ARCHITECTURE behavioral3 OF flipflop IS BEGINPROCESSBEGIN WAIT UNTIL rising_edge(Clock) ; Q <= D ; END PROCESS ; END behavioral3 ; D flip-flopD Q Clock16LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop_ar IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop_ar ;ARCHITECTURE behavioral OF flipflop_ar IS BEGINPROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= '0' ; ELSIF rising_edge(Clock) THEN Q <= D ; END IF ; END PROCESS ;END behavioral ; D flip-flop with asynchronous resetD Q Clock Resetn17LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop_sr IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop_sr ;ARCHITECTURE behavioral OF flipflop_sr IS BEGINPROCESS(Clock) BEGIN IF rising_edge(Clock) THEN IF Resetn = '0' THEN Q <= '0' ; ELSEQ <= D ; END IF ; END IF;END PROCESS ;END behavioral ; D flip-flop with synchronous resetD Q Clock Resetn18Asychronous vs. Synchronous•In the IF loop, asynchronous items are•Before the rising_edge(Clock) statement•In the IF loop, synchronous items are•After the rising_edge(Clock) statement198-bit register with asynchronous resetLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY reg8 ISPORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;Resetn, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;END reg8 ;ARCHITECTURE behavioral OF reg8 ISBEGINPROCESS ( Resetn, Clock )BEGINIF Resetn = '0' THENQ <= "00000000" ;ELSIF rising_edge(Clock) THENQ <= D ;END IF ;END PROCESS ;END behavioral ;`ResetnClockreg88 8D Q20N-bit register with asynchronous resetLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY regn ISGENERIC ( N : INTEGER := 16 ) ;PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;Resetn, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;END regn ;ARCHITECTURE behavioral OF regn ISBEGINPROCESS ( Resetn, Clock )BEGINIF Resetn = '0' THENQ <= (OTHERS => '0') ;ELSIF rising_edge(Clock) THENQ <= D ;END IF ;END PROCESS ;END behavioral ;ResetnClockregnN ND Q21A