ECE 545 Project 1 Introduction & SpecificationSchedule of Projects (1)Schedule of Projects (2)All Projects – Honor Code RulesOptimization CriteriaProject 1 - Platform & toolsProject 1 - Final DeliverablesFinal Report (1)Final Report (2)Final Report (3)Slide 11Slide 12Required readingSlide 14Slide 15Slide 16RC6Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40ECE 545 Project 1Introduction & SpecificationSchedule of Projects (1)Project 1 RTL design for FPGAs (20 points)Due date: Monday, November 21, noonCheckpoints: Monday, October 31, noon - execution unit Monday, November 7, noon - control unit Monday, November 14, noon - testbench & verificationProject 2 RTL design for standard-cell ASICs (10 points)Due date: Monday, December 5, noonSchedule of Projects (2)Project 3 Behavioral modeling (15 points)Due date: Monday, December 19, noonAll Projects – Honor Code Rules•Using somebody’s else code and presenting it as your own is a serious Honor Code violation and may result in an F grade for the entire course.•All students are expected to write and debug their codes individually.•Students are encouraged to help and support each other in all problems related to the–basic understanding of the problem–operation of the CAD tools.Optimization CriteriaMaximum ratioThroughput divided byTotal Circuit Area [CLB slices] Project 1Project 2Throughput divided byTotal Circuit Area [m2]Project 1 - Platform & toolsTarget devices: Xilinx FPGA Spartan 2 familyTools:VHDL Simulation: Aldec Active HDL or ModelSimVHDL Synthesis: Synplify ProImplementation: Xilinx ISEProject 1 - Final Deliverables1. All block diagrams and ASM chartsdescribing the entire circuit and its components. 2. All synthesizable VHDL source codes.3. All testbenches used to verify the operation of the entire circuit and its components, and the correspondinginput files containing test vectors, and output files containing results.4. Timing waveforms demonstrating the correct operationof the entire circuit and its components.5. Final report.Final Report (1)1. Short description of the block diagrams and ASM charts. Discussion of any alternative architectures and solutions.2. List of source codes and a short description of major modules.3. Source of test vectors and a way of generating these test vectors.4. Format of input & output files. Short description of a testbench.Final Report (2)5. Results•resource utilization (CLB slices, LUTs, FFs,BRAMs, etc.)•post-synthesis timing•clock frequency•throughput•latency•critical path•post placing & routing timing•clock frequency•throughput•latency•critical pathFinal Report (3)6. Discussion of the obtained results and and any optimizations applied in order to obtain the maximum throughput to area ratio.7. Speed-up vs. software implementation.8. Discussion of dependence of results on parameters of the application.9. Deviations from the original specification, encountered problems, and unresolved issues.Two topics from two different areas to choose fromCryptography:Digital Signal Processing:RC6 encryption and decryptionInfinite Impulse Response FilterRC6 Encryption & DecryptionRequired readingR. Rivest, M.J.B. Robshaw, R. Sidney, and Y.L. Yin“The RC6 Block Cipher”Sections 1, 2, and AppendixSource of test vectors“The RC6 Block Cipher,” AppendixReference C implementationCipherMessage / CiphertextCiphertext / MessageCryptographicKeym bitsm bitsk bitsEncrypt/Decrypt1 bitSecret-Key Cipherskey of Alice and Bob - KABkey of Alice and Bob - KABAliceBobNetworkEncryptionDecryptionInitial transformationFinal transformationr timesRound Key[i]i:=i+1Round Key[0]i:=1i < rCipher RoundRound Key[#rounds+1]Typical Flow Diagram of a Secret-Key CipherRC6Ron Rivest, MIT, 1998• variable key length - k• variable i/o block size - m• variable number of rounds - r• simple description(Ron’s Code 6, Rivest’s Cipher 6)RC6 w/r/bw - word size in bitsinput/output block size, m = 4 words = 4w bits Typical values: w=32  128-bit input/output block w=64  256-bit input/output blockr - number of roundsb - key size in byteskey size in bits, k = 8b bits 0  b  255w = 16, 32, 64RC6 32/20/16 128 bit input/output block 20 rounds128 bit keyMost commonly used set of parametersHigh-level view of the RC6 cipherenc_deckey, Kdata_in (message/ciphertext block)data_out (ciphertext/message block)Encryption/decryptionunitMemoryof roundkeysKeyschedulingm=4wm=4w8bwS[0..2r+3]S[i]to be implementedBasic OperationsX, Y - concatenation of X and Y (bits of X followed by bits of Y)X  Y - XORX <<< Y - X rotated by Y positions to the leftX >>> Y - X rotated by Y positions to the rightX + Y - addition without carry (addition modulo 2w)X + Y - subtraction without borrow (subtraction modulo 2w)X * Y - multiplication mod 2wEncryptionInput: (A, B, C, D) Table S[0..2r+3]B = B + S[0]D = D + S[1]for i= 1 to r do { t= (B*(2B+1)) <<< log2w u= (D*(2D+1)) <<< log2w A= ((At) <<< u) + S[2i] C= ((Cu) <<< t) + S[2i+1] (A, B, C, D) = (B, C, D, A) }A = A + S[2r+2]C = C + S[2r+3]Output: (A, B, C, D)RC6DecryptionInput: (A, B, C, D) Table S[0..2r+3]C = C – S[2r+3]A = A – S[2r+2]for i= r downto 1 do { (A, B, C, D) = (D, A, B, C) u= (D*(2D+1)) <<< log2w t= (B*(2B+1)) <<< log2w C= ((C – S[2i+1]) >>> t)u A= ((A – S[2i]) >>> u)t }D = D – S[1]B = B – S[0]Output (A, B, C, D)Encryption/decryptionunitwith control & i/o interfaceclockresetenc_decdata_indata_availabledata_readmS_ikey_availablekey_readKey memory unitdata_outwritefullmround numberround key(s)Required interfacewreadyRC6Implementation Hintsregistercombinationallogicone roundmultiplexerBasic iterative architectureof the encryption/decryption unitround keysenc_decINOUTM1C1M2C2M3Basic iterative architecture: Timingr · clock_periodCLKImplementation of arithmetic operationsAddition, subtraction, and multiplicationcan be implemented using +, –, and * in VHDLYour own custom architectures can be used for optimizations, but are not required or expected.Infinite Impulse Response FilterRequired readingU. M. Baese, Digital Signal Processing with Field Programmable Gate Arrays,Chapter 4, Infinite