ECE 545 Lecture 7 Variables Functions Memory File I O ECE 545 Introduction to VHDL George Mason University Variables ECE 545 Introduction to VHDL 2 Variable Example 1 LIBRARY ieee USE ieee std logic 1164 all ENTITY Numbits IS PORT X Count END Numbits ECE 545 Introduction to VHDL IN STD LOGIC VECTOR 1 TO 3 OUT INTEGER RANGE 0 TO 3 3 Variable Example 2 ARCHITECTURE Behavior OF Numbits IS BEGIN PROCESS X count the number of bits in X equal to 1 VARIABLE Tmp INTEGER BEGIN Tmp 0 FOR i IN 1 TO 3 LOOP IF X i 1 THEN Tmp Tmp 1 END IF END LOOP Count Tmp END PROCESS END Behavior ECE 545 Introduction to VHDL 4 Variables features Can only be declared within processes and subprograms functions procedures Initial value can be explicitly specified in the declaration When assigned take an assigned value immediately Variable assignments represent the desired behavior not the structure of the circuit Should be avoided or at least used with caution in a synthesizable code ECE 545 Introduction to VHDL 5 Variables vs Signals ECE 545 Introduction to VHDL 6 Variable Example ARCHITECTURE Behavior OF Numbits IS BEGIN PROCESS X count the number of bits in X equal to 1 VARIABLE Tmp INTEGER BEGIN Tmp 0 FOR i IN 1 TO 3 LOOP IF X i 1 THEN Tmp Tmp 1 END IF END LOOP Count Tmp END PROCESS END Behavior ECE 545 Introduction to VHDL 7 Incorrect Code using Signals ARCHITECTURE Behavior OF Numbits IS SIGNAL Tmp INTEGER RANGE 0 TO 3 BEGIN PROCESS X count the number of bits in X equal to 1 BEGIN Tmp 0 FOR i IN 1 TO 3 LOOP IF X i 1 THEN Tmp Tmp 1 END IF END LOOP Count Tmp END PROCESS END Behavior ECE 545 Introduction to VHDL 8 Parity generator entity library ieee use ieee std logic 1164 all entity oddParityLoop is generic width integer 8 port ad in std logic vector width 1 downto 0 oddParity out std logic end oddParityLoop ECE 545 Introduction to VHDL 9 Parity generator architecture using variables architecture behavioral of oddParityLoop is begin process ad variable loopXor std logic begin loopXor 0 for i in 0 to width 1 loop loopXor loopXor xor ad i end loop oddParity loopXor end process end behavioral ECE 545 Introduction to VHDL 10 Parity generator architecture using signals architecture dataflow of oddParityGen is signal genXor std logic vector width downto 0 begin genXor 0 0 parTree for i in 1 to width generate genXor i genXor i 1 XOR ad i 1 end generate oddParity genXor width end dataflow ECE 545 Introduction to VHDL 11 N bit NAND library ieee use ieee std logic 1164 all ENTITY NANDn IS GENERIC n INTEGER 4 PORT X IN STD LOGIC VECTOR 1 TO n Y OUT STD LOGIC END NANDn ECE 545 Introduction to VHDL 12 N bit NAND architecture using variables ARCHITECTURE behavioral1 OF NANDn IS BEGIN PROCESS X VARIABLE Tmp STD LOGIC BEGIN Tmp X 1 AND bits FOR i IN 2 TO n LOOP Tmp Tmp AND X i END LOOP AND bits Y NOT Tmp END PROCESS END behavioral1 ECE 545 Introduction to VHDL 13 Incorrect N bit NAND architecture using signals ARCHITECTURE behavioral2 OF NANDn IS SIGNAL Tmp STD LOGIC BEGIN PROCESS X BEGIN Tmp X 1 AND bits FOR i IN 2 TO n LOOP Tmp Tmp AND X i END LOOP AND bits Y NOT Tmp END PROCESS END behavioral2 ECE 545 Introduction to VHDL 14 Correct N bit NAND architecture using signals ARCHITECTURE dataflow1 OF NANDn IS SIGNAL Tmp STD LOGIC VECTOR 1 TO n BEGIN Tmp 1 X 1 AND bits FOR i IN 2 TO n LOOP Tmp i Tmp i 1 AND X i END LOOP AND bits Y NOT Tmp n END dataflow1 ECE 545 Introduction to VHDL 15 Correct N bit NAND architecture using signals ARCHITECTURE dataflow2 OF NANDn IS SIGNAL Tmp STD LOGIC VECTOR 1 TO n BEGIN Tmp OTHERS 1 Y 0 WHEN X Tmp ELSE 1 END dataflow2 ECE 545 Introduction to VHDL 16 Functions ECE 545 Introduction to VHDL 17 Functions basic features Functions never modify parameters passed to them always return a single value as a result are always used in some expression and not called on their own ECE 545 Introduction to VHDL 18 User defined Functions ECE 545 Introduction to VHDL 19 Function example 1 library IEEE use IEEE std logic 1164 all ENTITY powerOfFour IS PORT X IN INTEGER Y OUT INTEGER END powerOfFour ECE 545 Introduction to VHDL 20 Function example 2 ARCHITECTURE behavioral OF powerOfFour IS FUNCTION Pow N Exp INTEGER RETURN INTEGER IS VARIABLE Result INTEGER 1 BEGIN FOR i IN 1 TO Exp LOOP Result Result N END LOOP RETURN Result END Pow BEGIN Y Pow X 4 END behavioral ECE 545 Introduction to VHDL 21 User defined Functions basic features User defined Functions are declared between the architecture declaration statement and the BEGIN statement of that architecture just like components are called using formal and actual parameters the same way as components may be defined in package bodies ECE 545 Introduction to VHDL 22 Package containing a function 1 LIBRARY IEEE USE IEEE std logic 1164 all PACKAGE specialFunctions IS FUNCTION Pow N Exp INTEGER RETURN INTEGER END specialFunctions ECE 545 Introduction to VHDL 23 Package containing a function 2 PACKAGE BODY specialFunctions IS FUNCTION Pow N Exp INTEGER RETURN INTEGER IS VARIABLE Result INTEGER 1 BEGIN FOR i IN 1 TO Exp LOOP Result Result N END LOOP RETURN Result END Pow END specialFunctions ECE 545 Introduction to VHDL 24 User defined Procedures ECE 545 Introduction to VHDL 25 Procedure example 1 library IEEE use IEEE std logic 1164 all use work decProcs all entity decoder is port decIn in std logic vector 1 downto 0 decOut out std logic vector 3 downto 0 end decoder ECE 545 Introduction to VHDL 26 Procedure example 2 architecture simple of decoder is procedure DEC2x4 inputs in std logic vector 1 downto 0 decode out std logic vector 3 downto 0 is begin case inputs is when 11 decode 1000 when 10 decode 0100 when 01 decode 0010 when 00 decode 0001 when others decode 0001 end case end DEC2x4 begin DEC2x4 decIn decOut end simple ECE 545 Introduction to VHDL 27 Memories ECE 545 Introduction to VHDL 28 Distributed RAM RAM16X1S A LUT equals 16x1 RAM Implements Single and DualPorts Cascade LUTs to increase RAM size Synchronous write Synchronous Asynchronous read Accompanying flip flops used for synchronous read ECE 545 Introduction to VHDL LUT CLB LUT configurable as Distributed RAM D WE WCLK A0 A1 A2 A3 O RAM32X1S D WE WCLK A0 A1 A2 A3 A4 LUT LUT or O RAM16X2S D0 D1 WE WCLK A0 A1 A2 A3 O0 O1 or RAM16X1D D WE WCLK A0 SPO A1 A2 A3 DPRA0 DPO DPRA1 DPRA2 DPRA3 29 RAM 16x1 1 library IEEE use IEEE STD LOGIC 1164 all library UNISIM use UNISIM all entity RAM 16X1 DISTRIBUTED is port CLK in STD LOGIC WE in STD LOGIC ADDR in STD LOGIC VECTOR 3 …