Building BlocksEntity DeclarationEntity Declaration with GenericsArchitecture BodyDeclaring a ComponentDeclaring a Component with GenericsComponent Instantiation (named association)Component Instantiation with Generics (named association)Component Instantiation (positional association)Building Blocks Entity Declaration Description Example entity entity_name is port ( [signal] identifier {, identifier}: [mode] signal_type {; [signal] identifier {, identifier}: [mode] signal_type}); end [entity] [entity_name]; entity register8 is port ( clk, rst, en: in std_logic; data: in std_logic_vector(7 downto 0); q: out std_logic_vector(7 downto 0); end register8; Entity Declaration with Generics Description Example entity entity-name is generic ( [signal] identifier {, identifier}: [mode] signal-type [:= static_expression] {; [signal] identifier {, identifier}: [mode] signal_type [:= static_expression] } ); port ( [signal] identifier {, identifier}: [mode] signal_type {; [signal] identifier {, identifier}: [mode] signal_type} ); end [entity] [entity_name] ; entity register_n is generic ( width: integer := 8); port ( clk, rst, en: in std_logic; data: in std_logic_vector(width-1 downto 0); q: out std_logic_vector(width-1 downto 0)) end register_n; Architecture Body Description Example architecture architecture_name of entity is type_declaration | signal _declaration | constant_declaration | component_declaration | alias_declaration | attribute_specification | subprogram_body begin {process_statement | concurrent_signal_assignment_statement | component_instantiation_statement | generate_statement end [architecture] [architecture_name]; architecture archregister8 of register8 is begin process (rst, clk) begin if (rst = ‘1’) then q <= (others => 0); elseif (clk’event and clk = ‘1’) then if (en = ‘1’) then q <= data; else q <= q; end if; end if; end process; end archregister8; architecture archfsm of fsm is type state)type is (st0, st1, st2); signal state: state_type; signal y, z: std_logic; begin process begin wait until clk’ = ‘1’; case state is when st0 => state <= st1; y <= ‘1’; when st1 => state <= st2; z <= ‘1’; when others => state <= st3; y <= ‘0’; z <= ‘0’; end case; end process; end archfsm;Declaring a Component Description Example component component_name port ( [signal] identifier {, identifier}: [mode] signal_type {; [signal] identifier {, identifier}: [mode] signal_type] ); end component [component_name] ; component register8 port ( c1k, rst, en: in std_logic ; data: in std_1ogic_vector(7 downto 0); q: out std_logic_vector(7 downto 0)); end component; Declaring a Component with Generics Description Example component component_name generic ( [signal] identifier {, identifier}: [mode] signal_type [: =static_expression] {; [signal] identifier {, identifier}: [mode] signal_type [ : =static_expression] ); port ( [signal] identifier {, identifier}: [mode] signal_type {; [signal] identifier {, identifier}: [mode] signal_type ); end component [component_name]; component register8 generic ( width: integer := 8 ); port ( clk, rst, en: in std_logic; data: in std_1ogic_vector(width-1 downto 0); q: out std_logic_vector (width-l downto 0)); end component; Component Instantiation (named association) Description Example instantiation_label: component_name port map ( port_name => signal_name | expression | variable_name | open {, port_name => signal_name | expression | variable_name | open}); architecture archreg8 of reg8 is signal clock, reset, enable: std_logic; signal data-in, data-out: std_logic_vector(T downto 0); begin first_reg8: register8 port map ( clk => clock, rst => reset, en => enable, data => data_in, q => data_out); end archreg8; Component Instantiation with Generics (named association) Description Example Instantiation_label: Component_name generic map( generic_name => signal_name | expression | variable_name | open {, generic_name => signal_name | expression | variable_name | open}) port map ( port_name => signal_name | expression | variable_name | open {, port_name => signal_name | expression | variable_name | open}); architecture archreg5 of reg5 is signal clock, reset, enable: std_logic; signal data_in, data_out: std_logic_vector(7 downto 0); begin first_reg5: register_n generic map (width => 5) --no semicolon here port map ( clk => clock , rst => reset, en => enable, data => data-in, q => data_out); end archreg5; Component Instantiation (positional association) Description Example instantiation_label: component_name port map (signal_name | expression | variable_name | open {, signal_name | expression | variable_name | open}); architecture archreg8 of reg8 is signal clock, reset, enable: std_logic; signal data_in, data_out: std_logic_vector(7 downto 0); begin first_reg8: register8 port map (clock, reset, enable, data_in, data_out); end archreg8;Component Instantiation with Generics (positional association) Description Example instantiation_lable: component_name generic map ( signal_name | expression | variable_name | open {, signal_name | expression | variable_name | open}) port map ( signal_name | expression | variable_name | open {, signal_name | expression | variable_name | open}); architecture archreg5 of reg5 is signal clock, reset, enable: std_logic; signal data_in, data_out: std_logic_vector(7