Introduction to FPGA Devices & ToolsFPGA DevicesWorld of Integrated CircuitsSlide 4Slide 5Which Way to Go?Other FPGA AdvantagesMajor FPGA VendorsXilinxXilinx FPGA FamiliesSlide 11Basic Spartan-II FPGA Block DiagramCLB StructureCLB Slice StructureLUT (Look-Up Table) FunctionalityDistributed RAMShift RegisterShift RegisterCarry & Control LogicFast Carry LogicAccessing Carry LogicBlock RAMSpartan-II Block RAM AmountsBlock RAM Port Aspect RatiosBasic I/O Block StructureIOB FunctionalityRouting ResourcesSpartan-II FPGA Family MembersSlide 29Virtex-II 1.5V ArchitectureVirtex-II 1.5VVirtex-II Block SelectRAMSlide 33FPGA ToolsDesign process (1)Design process (2)Slide 37Simulation ToolsSlide 39Slide 40Synthesis ToolsSlide 42Features of synthesis toolsImplementationSlide 45TranslationSample UCF FilePin AssignmentParallel Port InterfaceConstraints EditorCircuit netlistMappingPlacingRoutingStatic Timing AnalyzerStatic Timing AnalysisSlide 57ConfigurationResources & Required ReadingSlide 60Hands-on SessionMLU: Block DiagramSlide 63Questions?ECE 545 – Introduction to VHDL George Mason UniversityIntroduction to FPGA Devices & ToolsECE 545 – Introduction to VHDL George Mason UniversityFPGA DevicesECE 545 – Introduction to VHDL 3World of Integrated CircuitsIntegrated CircuitsFull-CustomASICsSemi-CustomASICsUserProgrammablePLD FPGAPAL PLA PMLLUT(Look-Up Table)MUX GatesECE 545 – Introduction to VHDL 4• designs must be sent for expensive and time consuming fabrication in semiconductor foundry• bought off the shelf and reconfigured by designers themselvesTwo competing implementation approachesASICApplication SpecificIntegrated CircuitFPGAField ProgrammableGate Array• designed all the way from behavioral description to physical layout• no physical layout design; design ends with a bitstream used to configure a deviceECE 545 – Introduction to VHDL 5Block RAMsBlock RAMsConfigurableLogicBlocksI/OBlocksWhat is an FPGA?BlockRAMsECE 545 – Introduction to VHDL 6Which Way to Go?Off-the-shelfLow development costShort time to marketReconfigurabilityHigh performanceASICs FPGAsLow powerLow cost inhigh volumesECE 545 – Introduction to VHDL 7Other FPGA Advantages•Manufacturing cycle for ASIC is very costly, lengthy and engages lots of manpower•Mistakes not detected at design time have large impact on development time and cost•FPGAs are perfect for rapid prototyping of digital circuits•Easy upgrades like in case of software•Unique applications•reconfigurable computingECE 545 – Introduction to VHDL 8Major FPGA VendorsSRAM-based FPGAs•Xilinx, Inc.•Altera Corp.•Atmel•Lattice SemiconductorFlash & antifuse FPGAs•Actel Corp.•Quick Logic Corp.ECE 545 – Introduction to VHDL 9XilinxPrimary products: FPGAs and the associated CAD softwareMain headquarters in San Jose, CAFabless* Semiconductor and Software CompanyUMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996}Seiko Epson (Japan)TSMC (Taiwan)Programmable Logic DevicesISE Alliance and Foundation Series Design SoftwareECE 545 – Introduction to VHDL 10Xilinx FPGA Families•Old families•XC3000, XC4000, XC5200•Old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern designs.•High-performance families•Virtex (0.22µm)•Virtex-E, Virtex-EM (0.18µm)•Virtex-II, Virtex-II PRO (0.13µm)•Low Cost Family•Spartan/XL – derived from XC4000•Spartan-II – derived from Virtex•Spartan-IIE – derived from Virtex-E•Spartan-3ECE 545 – Introduction to VHDL 11ECE 545 – Introduction to VHDL 12Basic Spartan-II FPGA Block DiagramECE 545 – Introduction to VHDL 13F5INCINCLKCECOUTDQCKSRECDQCKRECOG4G3G2G1Look-UpTableCarry&ControlLogicOYBYF4F3F2F1XBXLook-UpTableBYSRSCarry&ControlLogicSLICECOUTDQCKSRECDQCKRECOG4G3G2G1Look-UpTableCarry&ControlLogicOYBYF4F3F2F1XBXLook-UpTableF5INBYSRSCarry&ControlLogicCINCLKCESLICECLB Structure•Each slice has 2 LUT-FF pairs with associated carry logic•Two 3-state buffers (BUFT) associated with each CLB, accessible by all CLB outputsECE 545 – Introduction to VHDL 14CLB Slice Structure•Each slice contains two sets of the following:•Four-input LUT•Any 4-input logic function,•or 16-bit x 1 sync RAM•or 16-bit shift register•Carry & Control•Fast arithmetic logic•Multiplier logic•Multiplexer logic•Storage element•Latch or flip-flop•Set and reset•True or inverted inputs•Sync. or async. controlECE 545 – Introduction to VHDL 15LUT (Look-Up Table) Functionality•Look-Up tables are primary elements for logic implementation•Each LUT can implement any function of 4 inputsx1x2x3x4yx1x2yLUTx1x2x3x4y0x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y01000101010011000x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y1111111111110000x1x2x3x4yx1x2x3x4yx1x2yx1x2yLUTx1x2x3x4y0x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y01000101010011000x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y01000101010011000x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y11111111111100000x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y1111111111110000ECE 545 – Introduction to VHDL 16RAM16X1SODWEWCLKA0A1A2A3RAM32X1SODWEWCLKA0A1A2A3A4RAM16X2SO1D0WEWCLKA0A1A2A3D1O0==LUTLUTorLUTRAM16X1DSPODWEWCLKA0A1A2A3DPRA0 DPODPRA1DPRA2DPRA3orDistributed RAM•CLB LUT configurable as Distributed RAM•A LUT equals 16x1 RAM•Implements Single and Dual-Ports•Cascade LUTs to increase RAM size•Synchronous write•Synchronous/Asynchronous read•Accompanying flip-flops used for synchronous readECE 545 – Introduction to VHDL 17D QCED QCED QCED QCELUTINCECLKDEPTH[3:0]OUTLUT=Shift Register•Each LUT can be configured as shift register•Serial in, serial out•Dynamically addressable delay up to 16 cycles•For programmable pipeline•Cascade for greater cycle delays•Use CLB flip-flops to add depthECE 545 – Introduction to VHDL 18Shift Register •Register-rich FPGA•Allows for addition of pipeline stages to increase throughput•Data paths must be balanced to keep desired functionality64Operation A4 Cycles 8 CyclesOperation B3 CyclesOperation