Timing Event-driven simulationSourcesSlide 3Timing Characteristics of Combinational CircuitsTiming Characteristics of Combinational Circuits (2)Timing Characteristics of Combinational Circuits (3)Timing Characteristics of Combinational Circuits (4)Timing Characteristics of Sequential Circuits (1)Timing Characteristics of Sequential Circuits (2)Critical Path (1)Critical Path (2)Clock JitterClock SkewDealing With Clock ProblemsSlide 15Physical data typesTime values (physical literals) - ExamplesTIME valuesUnits of timeValues of the type TIMEArithmetic operations on values of the type TIMESlide 22Propagation delay in VHDL - ExamplePropagation delay - ExampleMLU: Block DiagramMLU - Architecture Body – Example 1MLU - Architecture Body – Example 2Delay constantsSlide 29Inertial delay modelInertial delay model - ExampleVHDL-87 Inertial delay modelVHDL-93 Enhanced inertial delay modelSlide 34Transport delay modelTransport delay model - ExampleOther delay modelsSlide 38Event list as a linked list structureEvent list as an array – Timing wheelNotationTop-level algorithmProcess entries for time t - Basic versionEvent-driven simulation - exampleSlide 45Process entries for time t – True events only version – Two-pass algorithmProcess entries for time t – True events only version – One-pass algorithmSlide 48Delta delayTwo-dimensional aspect of timeSlide 51Slide 52Transaction vs. EventProperties of signalsSlide 55Signal attributes (1)Signal attributes (2)Signal attributes (3)Detecting setup time violationSlide 60Synthesis processSDF fileNetlist from the synthesis toolECE 545 – Introduction to VHDL George Mason UniversityTimingEvent-driven simulationECE 545Lecture 8ECE 545 – Introduction to VHDL 2Sources•A. Deway, Analysis and Design of Digital Systems with VHDL, Chapters 15, VHDL Technology•M. Abramovici, M. Breuer, A. Friedman Chapter 3.10, Gate-Level Event Driven Simulation• P. Ashenden, The Designer’s Guide to VHDL, Chapter 5.3Signal AttributesDelta DelaysTransport and Inertial Delay MechanismsECE 545 – Introduction to VHDL 3Timing of digital circuitsECE 545 – Introduction to VHDL 4Timing Characteristics of Combinational Circuits•Combinational Circuits Are Characterized by Propagation Delays•through logic components (gates, LUTs)•through interconnects (routing delays)tp LUTtp routingLUT LUT LUTTotal propagation delay through combinational logicECE 545 – Introduction to VHDL 5Timing Characteristics of Combinational Circuits (2)•Total Propagation Delay of Logic Depends on the Number of Logic Levels and Delays of Logic Components•Number of logic levels is the number of logic components (gates, LUTs) the signal propagates through•Routing Delays Depend on:•Length of interconnects•FanoutECE 545 – Introduction to VHDL 6Timing Characteristics of Combinational Circuits (3)•Fanout – Number of Inputs Connected to One Output•Each inputs has its capacitance•Fast switching of outputs with high fanout requires higher currents and strong driversLUT LUTLUTLUTECE 545 – Introduction to VHDL 7Timing Characteristics of Combinational Circuits (4)•In Current Technologies Routing Delays Make 50-70% of the Total Propagation DelaysECE 545 – Introduction to VHDL 8Timing Characteristics of Sequential Circuits (1)•Timing Features of Flip-flops•Setup time tS – minimum time the input has to be stable before the rising edge of the clock•Hold time tH – minimum time the input has to be stable after the rising edge of the clock•Propagation delay tP – time to propagate input to output after the rising edge of the clockECE 545 – Introduction to VHDL 9Timing Characteristics of Sequential Circuits (2)D QclkclkDQtStHtPInput D must remain stable during this intervalInput D can freely change during this intervalECE 545 – Introduction to VHDL 10Critical Path (1)•Critical Path – The Longest Path From Outputs of Registers to Inputs of RegistersD QinclkD QouttP logictCritical = tP FF + tP logic + tS FFECE 545 – Introduction to VHDL 11Critical Path (2)•Min. Clock Period = Length of The Critical Path•Max. Clock Frequency = 1 / Min. Clock PeriodECE 545 – Introduction to VHDL 12Clock Jitter•Rising Edge of The Clock Does Not Occur Precisely Periodically•May cause faults in the circuitclkECE 545 – Introduction to VHDL 13Clock Skew•Rising Edge of the Clock Does Not Arrive at Clock Inputs of All Flip-flops at The Same TimeD QinclkD QoutdelayD QinclkD QoutdelayECE 545 – Introduction to VHDL 14Dealing With Clock Problems•Use Only Dedicated Clock Nets for Clock Signals•Do Not Put Any Logic in Clock NetsECE 545 – Introduction to VHDL 15Specifying time in VHDLECE 545 – Introduction to VHDL 16Physical data types Types representing physical quantities, such as time, voltage, capacitance, etc. are referred in VHDL as physical data types. TIME is the only predefined physical data type. Value of the physical data type is called a physical literal.ECE 545 – Introduction to VHDL 17Time values (physical literals) - Examples7 ns1 minmin10.65 us10.65 fsUnit of time(dimension)SpaceNumeric valueECE 545 – Introduction to VHDL 18TIME valuesNumeric value can be an integer or a floating point number. Numeric value is optional. If not given, 1 isimplied.Numeric value and dimension MUST beseparated by a space.ECE 545 – Introduction to VHDL 19Units of timeUnit DefinitionBase Unitfs femtoseconds (10-15 seconds)Derived Unitsps picoseconds (10-12 seconds)ns nanoseconds (10-9 seconds)us microseconds (10-6 seconds)ms miliseconds (10-3 seconds)sec secondsmin minutes (60 seconds)hr hours (3600 seconds)ECE 545 – Introduction to VHDL 20Values of the type TIMEValue of a physical literal is defined in termsof integral multiples of the base unit, e.g. 10.65 us = 10,650,000,000 fs10.65 fs = 10 fsSmallest available resolution in VHDL is 1 fs.Smallest available resolution in simulation can beset using a simulator command or parameter.ECE 545 – Introduction to VHDL 21Arithmetic operations on values of the type TIMEExamples: 7 ns + 10 ns = 17 ns 1.2 ns – 12.6 ps = 1187400 fs 5 ns * 4.3 = 21.5 ns 20 ns / 5ns = 4ECE 545 – Introduction to VHDL 22Propagation delay in VHDLECE 545 – Introduction to VHDL 23Propagation delay in VHDL - Exampleentity MAJORITY isport (A_IN, B_IN, C_IN : in STD_LOGIC; Z_OUT : out STD_LOGIC);end MAJORITY;architecture DATA_FLOW of MAJORITY isbeginZ_OUT <= (not A_IN and B_IN and C_IN) or(A_IN and not