Slide 1Required readingSimple TestbenchAdvanced TestbenchSlide 5Slide 6Slide 7AssertAssert - syntaxAssert – Examples (1)Assert – Examples (2)Assert – Examples (3)Report - syntaxReport - ExamplesSlide 15Generating reports in the message windowSlide 17RecordsSlide 19Variable – Example (1)Variable – Example (2)Variables - featuresSlide 23Testbench (1)Testbench (2)Testbench (3)Testbench (4)Testbench (5)Slide 29File I/O ExampleDesign Under Test (1)Design Under Test (2)Test vector file (1)Test vector file (2)Methodology to test vectors from fileSlide 36Slide 37Slide 38Slide 39Testbench (6)Simulation WaveformHex formatNote on test fileGeorge Mason UniversityECE 545Lecture 10Advanced Testbenches2Required reading•Sundar Rajan, Essential VHDL: RTL Synthesis Done RightChapter 14, starting from “Design Verification”3Simple TestbenchProcessesGeneratingInputStimuli Design Under Test (DUT)Outputs Observedas Timing Waveforms4Advanced TestbenchProcessesGeneratingInputStimuli Design Under Test (DUT)ProcessComparingActual Outputsvs.Expected OutputsDesignCorrect/IncorrectYes/NoTestvector file(s)5SourceofRepresentativeInputsVHDL DesignManual CalculationsorReference Software Implementation(C, Java, Matlab )Expected OutputsActual Outputs= ?InputsPossible Sources of Expected Outputs6Test vectorsSet of pairs: {Input i, Expected Output i}Input 1, Expected Output 1Input 2, Expected Output 2……………………………Input N, Expected Output NTest vectors can be: - defined in the testbench source file - stored in a data file7ECE 448 – FPGA and ASIC Design with VHDLAsserts & Reports8AssertAssert is a non-synthesizable statementwhose purpose is to write out messageson the screen when problems are foundduring simulation.Depending on the severity of the problem,The simulator is instructed to continuesimulation or halt.9Assert - syntaxASSERT condition[REPORT "message“][SEVERITY severity_level ];The message is written when the condition is FALSE.Severity_level can be: Note, Warning, Error (default), or Failure.10Assert – Examples (1)assert initial_value <= max_value report "initial value too large" severity error;assert packet_length /= 0 report "empty network packet received" severity warning;assert false report "Initialization complete" severity note;11Assert – Examples (2)-- suppose VHDL model is supposed to generate data -- with even parity with ack_test:wait until ack_test = '1'; parity := test_data(3) XOR test_data(2) XOR test_data(1) XOR test_data(0); assert parity = '0' report "Parity Error" severity error; R_test <= '0';12Assert – Examples (3)-- used in modeling flip-flops to check for timing problemscheck: process begin wait until clk'event and clk='1'; assert D'stable(setup_time) report "Setup Time Violation" severity error; wait for hold_time; assert D'stable(hold_time) report "Hold Time Violation" severity error; end process check;13Report - syntaxREPORT "message"[SEVERITY severity_level ];The message is always written.Severity_level can be: Note (default), Warning, Error, or Failure.14Report - Examplesreport "Initialization complete";report "Current time = " & time'image(now);report "Incorrect branch" severity error;15library IEEE;use IEEE.STD_LOGIC_1164.all;entity example_1_tb isend example_1_tb;architecture behavioral of example_1_tb issignal clk : std_logic := '0';begin clk <= not clk after 100 ns;processbeginwait for 1000 ns;report "Initialization complete";report "Current time = " & time'image(now); wait for 1000 ns;report "SIMULATION COMPLETED" severity failure;end process;end behavioral;Report - Examples16Generating reports in the message windowreports: process(clk_trigger) begin if (clk_trigger = '0' and clk_trigger'EVENT) then case segments iswhen seg_0 => report time'image(now) & ": 0 is displayed" ;when seg_1 => report time'image(now) & ": 1 is displayed" ;when seg_2 => report time'image(now) & ": 2 is displayed" ;when seg_3 => report time'image(now) & ": 3 is displayed" ;when seg_4 => report time'image(now) & ": 4 is displayed" ;when seg_5 => report time'image(now) & ": 5 is displayed" ;when seg_6 => report time'image(now) & ": 6 is displayed" ;when seg_7 => report time'image(now) & ": 7 is displayed" ;when seg_8 => report time'image(now) & ": 8 is displayed" ;when seg_9 => report time'image(now) & ": 9 is displayed" ; end case; end if;end process;17ECE 448 – FPGA and ASIC Design with VHDLRecords18Recordstype opcodes is (add, sub, and, or);type reg_number is range 0 to 8;type instruction is recordopcode : opcodes;source_reg1 : reg_number;source_reg2 : reg_number;dest_reg : reg_number;end record instruction;constant add_instr_1_3 : instruction:=(opcode => add, source_reg1 | dest_reg => 1, source_reg2 => 3);19ECE 448 – FPGA and ASIC Design with VHDLVariables20Variable – Example (1)LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY Numbits ISPORT ( X : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; Count : OUT INTEGER RANGE 0 TO 16) ;END Numbits ;21Variable – Example (2)ARCHITECTURE Behavior OF Numbits ISBEGINPROCESS(X) – count the number of bits in X equal to 1VARIABLE Tmp: INTEGER;BEGIN Tmp := 0; FOR i IN 15 DOWNTO 0 LOOP IF X(i) = ‘1’ THEN Tmp := Tmp + 1; END IF; END LOOP; Count <= Tmp;END PROCESS;END Behavior ;22Variables - features•Can only be declared within processes and subprograms (functions & procedures)•Initial value can be explicitly specified in the declaration•When assigned take an assigned value immediately•Variable assignments represent the desired behavior, not the structure of the circuit•Should be avoided, or at least used with caution in a synthesizable code23ECE 448 – FPGA and ASIC Design with VHDLUsing Arrays of Test VectorsIn Testbenches24Testbench (1)LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY sevenSegmentTB isEND sevenSegmentTB;ARCHITECTURE testbench OF sevenSegmentTB ISCOMPONENTsevenSegment PORT ( bcdInputs : IN STD_LOGIC_VECTOR (3 DOWNTO 0); seven_seg_outputs : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); );end COMPONENT;CONSTANT PropDelay: time := 40 ns;CONSTANT SimLoopDelay: time := 10 ns;25Testbench (2)TYPE vector IS RECORD bcdStimulus: STD_LOGIC_VECTOR(3 downto 0); sevSegOut: STD_LOGIC_VECTOR(6 downto 0);END RECORD;CONSTANT NumVectors: INTEGER:= 10;TYPE vectorArray is ARRAY (0 TO NumVectors - 1) OF vector;CONSTANT vectorTable: vectorArray := ( (bcdStimulus => "0000", sevSegOut => "0000001"), (bcdStimulus =>