Data Flow Modeling of Combinational LogicResourcesRegister Transfer Level (RTL) Design DescriptionSlide 4VHDL Design StylesSlide 6Slide 7Slide 8Slide 9Slide 10Logic OperatorsNo Implied PrecedenceConcatenationRotations in VHDLArithmetic Operators in VHDL (1)Arithmetic Operators in VHDL (2)Slide 17Conditional concurrent signal assignmentOperatorsPriority of logic and relational operatorsTri-state Buffer – example (1)Tri-state Buffer – example (2)Slide 23Selected concurrent signal assignmentAllowed formats of choices_kAllowed formats of choice_k - exampleSlide 27MLU: Block DiagramMLU: Entity DeclarationMLU: Architecture Declarative SectionMLU - Architecture BodySlide 32For Generate StatementSlide 34PARITY: Block DiagramPARITY: Entity DeclarationSlide 37PARITY: ArchitecturePARITY: Block Diagram (2)PARITY: Architecture (2)ECE 545 – Introduction to VHDL George Mason UniversityData Flow Modeling of Combinational LogicECE 545Lecture 3bECE 545 – Introduction to VHDL 2Resources• Volnei A. Pedroni, Circuit Design with VHDLChapter 5, Concurrent CodeChapter 4.1, Operators• Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 3, Gates, Decoders and Encoders (see errata at http://www.vahana.com/bugs.htm)ECE 545 – Introduction to VHDL 3Register Transfer Level (RTL) Design Description Combinational Logic Combinational LogicRegisters…Today’s TopicECE 545 – Introduction to VHDL 4DescribingCombinational LogicUsing Dataflow Design StyleECE 545 – Introduction to VHDL 5VHDL Design StylesComponents andinterconnectsstructuralVHDL Design StylesdataflowConcurrent statementsbehavioral• Registers• State machines• Test benchesSequential statementsECE 545 – Introduction to VHDL 6Data-flow VHDL• concurrent signal assignment ()• conditional concurrent signal assignment (when-else)• selected concurrent signal assignment (with-select-when)• generate scheme for equations (for-generate)Major instructionsConcurrent statementsECE 545 – Introduction to VHDL 7Data-flow VHDL• concurrent signal assignment ()• conditional concurrent signal assignment (when-else)• selected concurrent signal assignment (with-select-when)• generate scheme for equations (for-generate)Major instructionsConcurrent statementsECE 545 – Introduction to VHDL 8Data-flow VHDL: Example0 0 0 1 0 1 1 1 c i 1 + 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 c i x i y i 00 01 11 100 1 x i y i c i 1 1 1 1 s i x i y i c i Å Å = 00 01 11 100 1 x i y i c i 1 1 1 1 c i 1 + x i y i x i c i y i c i + + = c i x i y i s i c i 1 + (a) Truth table (b) Karnaugh maps (c) Circuit 0 1 1 0 1 0 0 1 s iECE 545 – Introduction to VHDL 9Data-flow VHDL: Example (1)LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY fulladd ISPORT ( x : IN STD_LOGIC ; y : IN STD_LOGIC ; cin : IN STD_LOGIC ; s : OUT STD_LOGIC ; cout : OUT STD_LOGIC ) ;END fulladd ;ECE 545 – Introduction to VHDL 10Data-flow VHDL: Example (2)ARCHITECTURE fulladd_dataflow OF fulladd ISBEGINs <= x XOR y XOR cin ;cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;END fulladd_dataflow ;ECE 545 – Introduction to VHDL 11Logic Operators•Logic operators•Logic operators precedenceand or nand nor xor not xnor notand or nand nor xor xnorHighestLowestonly in VHDL-93ECE 545 – Introduction to VHDL 12 Wanted: y = ab + cdIncorrecty <= a and b or c and d ; equivalent toy <= ((a and b) or c) and d ;equivalent toy = (ab + c)dCorrecty <= (a and b) or (c and d) ;No Implied PrecedenceECE 545 – Introduction to VHDL 13ConcatenationSIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL c, d, e, f: STD_LOGIC_VECTOR(7 DOWNTO 0);a <= ”0000”; b <= ”1111”; c <= a & b; -- c = ”00001111”d <= ‘0’ & ”0001111”; -- d <= ”00001111”e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ & ‘1’ & ‘1’; -- e <= ”00001111”f <= (‘0’,‘0’,‘0’,‘0’,‘1’,‘1’,‘1’,‘1’) ; -- f <= ”00001111”ECE 545 – Introduction to VHDL 14Rotations in VHDLa(3) a(2)a(1)a(0)a(2) a(1) a(0) a(3)a<<<1a_rotL <= a(2 downto 0) & a(3)ECE 545 – Introduction to VHDL 15Arithmetic Operators in VHDL (1)To use basic arithmetic operations involving std_logic_vectors you need to include thefollowing library packages:LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;orUSE ieee.std_logic_signed.all;ECE 545 – Introduction to VHDL 16Arithmetic Operators in VHDL (2)You can use standard +, - operatorsto perform addition and subtraction: signal A : STD_LOGIC_VECTOR(3 downto 0); signal B : STD_LOGIC_VECTOR(3 downto 0); signal C : STD_LOGIC_VECTOR(3 downto 0); …… C <= A + B;ECE 545 – Introduction to VHDL 17Data-flow VHDL• concurrent signal assignment ()• conditional concurrent signal assignment (when-else)• selected concurrent signal assignment (with-select-when)• generate scheme for equations (for-generate)Major instructionsConcurrent statementsECE 545 – Introduction to VHDL 18Conditional concurrent signal assignmenttarget_signal <= value1 when condition1 else value2 when condition2 else . . . valueN-1 when conditionN-1 else valueN;When - Else.…Value NValue N-1Condition N-1Condition 2Condition 1Value 2Value 1Target Signal…010101ECE 545 – Introduction to VHDL 19Operators•Relational operators•Logic and relational operators precedence= /= < <= > >= not= /= < <= > >=and or nand nor xor xnorHighestLowestECE 545 – Introduction to VHDL 20 compare a = bcIncorrect … when a = b and c else …equivalent to … when (a = b) and c else …Correct … when a = (b and c) else …Priority of logic and relational operatorsECE 545 – Introduction to VHDL 21Tri-state Buffer – example (1)LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY tri_state IS PORT ( ena: IN STD_LOGIC; input: IN STD_LOGIC_VECTOR(7 downto 0); output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );END tri_state;ECE 545 – Introduction to VHDL 22Tri-state Buffer – example (2)ARCHITECTURE tri_state_dataflow OF tri_state ISBEGIN output <= input WHEN (ena = ‘0’) ELSE