ECE-545, Introduction to VHDLIntroductionAdministrativeSlide 4Slide 5GradingHomeworksRequired TextbookLocal web ResourcesOptional ResourcesSlide 11Honor CodeRASSPRASSP RoadmapWhy HDL?AdvantagesMultiple Capabilities Reduce Board Size/costDesign MotivationBreadth MotivationValue of ModelsSysGen Design to FPGAFPGA Design ProcessLengua Franca MotivationLegacy MotivationNeed for HDLTypical FPGA Xilinx Virtex XCV 1000What Is Inside A Virtex Slice?Breadth of HDLDepth of HDLVHDLA Brief History of VHDLSlide 32Slide 33Slide 34Languages Other Than VHDLABELALTERAAHPLCDLCONLANIDLISPSTEGASTI-HDLVERILOGZEUSDifferent Representation ModelsGajski and Kuhn’s Y ChartFunctional ModelBehavioral ModelFunctional & Behavioral DescriptionsDataflow ModelStructural ModelStructural DescriptionsSlide 55Physical ModelProcessing of ModelsVHDL ModelVHDL Design ExampleVHDL Design Example Entity DeclarationVHDL Design Example Functional SpecificationVHDL Design Example Behavioral SpecificationVHDL Design Example Data Flow SpecificationVHDL Design Example Structural SpecificationVHDL Design Example Structural Specification (Cont.)Slide 66VHDL Model ComponentsSlide 68ProcessSlide 70Entity DeclarationsEntity ExampleEntity Declarations Port ClauseEntity Declarations Port Clause (Cont.)Slide 75Entity Declarations Generic ClauseBehavioral DescriptionsGeneric ClauseArchitecture BodiesSlide 80Slide 81Architecture Body, e.g.Lexical Elements of VHDLSlide 84Slide 85Slide 86Slide 87Slide 88Slide 89Slide 90Slide 91VHDL SyntaxSlide 93Slide 94Slide 95Slide 96Slide 97Slide 98VHDL Lecture 101/14/19 ©KJH, 545_a 1ECE-545, Introduction to VHDLProf. K. J. HintzDepartment of Electrical and Computer EngineeringGeorge Mason University01/14/19 ©KJH, 545_a 2IntroductionAdministrationWhy VHDL?Alternative languagesModels of Digital SystemsBasic Structure of VHDLVHDL Lexicography01/14/19 ©KJH, 545_a 3AdministrativeInstructor: Prof. K. J. HintzCourse Information–My home page http://cpe.gmu.edu/~khintz–Computer Engineering web site»http://cpe.gmu.edu»http://129.174.140.501/14/19 ©KJH, 545_a 4AdministrativeOffice–Science and Technology II, Room 225Office Hours–See home page–Other Times by AppointmentOffice Phone–(703)993-1592 (Answering Machine)01/14/19 ©KJH, 545_a 5AdministrativeEmail–[email protected]Students with Disabilities–If you need special assistance, please inform me soon so that we can work something out.A milestone chart and homework assignments are available on the 545 web site.01/14/19 ©KJH, 545_a 6GradingHW 25%Mid-Term Exam 35%Final Exam 40%–Optional semester long project01/14/19 ©KJH, 545_a 7HomeworksHomeworks Require Use of MGC VHDLMentor Graphics, ModelSim–cpe02.gmu.edu, Computer Engineering LabX-terminalsOff-campus access on PCs available through VNC, Linux, Cygus01/14/19 ©KJH, 545_a 8Required TextbookThe Designer’s Guide to VHDL–Peter J. Ashenden–Morgan-Kaufman–ISBN 1-55860-270-4 (paperback)–LOC TK7888.3.A863–Dewey Decimal 621.39’2--dc20–2nd Edition, Copyright 200201/14/19 ©KJH, 545_a 9Local web ResourcesIEEE Interactive VHDL Tutorial–On-line on Computer Engineering Home page–http://cpe.gmu.edu–password protectedIEEE Standard 1076-1993–On-line on Computer Engineering Home page–password protected01/14/19 ©KJH, 545_a 10Optional ResourcesCypress Semiconductor (Warp release 6.x)–http://www.cypress.com–PC-based–$99 with textbook, possibly free–Oriented towards Their PLD & FPGA devices–VHDL Subset simulatorXilinx FPGA, ISE–http://www.xilinx.com–Student edition, Prentice-Hall–Schematic, FSM, VHDL01/14/19 ©KJH, 545_a 11Optional ResourcesAshenden CDROM (2nd Edition)–Source Code–FTL Simulator01/14/19 ©KJH, 545_a 12Honor CodeYou Are Encouraged to Collaborate With Other StudentsExams Are Closed Book, Closed Notes, and the Normal Honor Code Applies to All Exams01/14/19 ©KJH, 545_a 13RASSPSome of the materials used in this course come from ARPA RASSP Program and are copyright–Rapid Prototyping of Application Specific Signal Processors Program–http://www.eda.org/rassp/Rest of materials are copyright K. J. Hintz01/14/19 ©KJH, 545_a 14RASSP Roadmap VHDL VHDLSYSTEMDEF.FUNCTIONDESIGNHW & SWPART.HWDESIGNSWDESIGNHWFABSWCODEINTEG.& TESTVIRTUAL PROTOTYPERASSP DESIGN LIBRARIES AND DATABASEPrimarilysoftwarePrimarilyhardwareHW & SW CODESIGNCopyright  1995, 1996 RASSP E&F01/14/19 ©KJH, 545_a 15Why HDL?Achieve Maximum Reliability With –Minimum cost–Minimum development timeAllows for Design Automation01/14/19 ©KJH, 545_a 16AdvantagesIndustry Is Moving to –FPGAs (Field Programmable Gate Array) for system prototypes and small volume applications–ASICs (Application Specific Integrated Circuits) for high-performance/high-volume SystemsReduces In-field Hardware Maintenance Due to Fewer Components and InterconnectsHigh-level Design Tools Are Becoming Available to Reduce the NRE Costs and Provide Quicker Turn Around01/14/19 ©KJH, 545_a 17Multiple Capabilities Reduce Board Size/cost01/14/19 ©KJH, 545_a 18Design MotivationDigital System Complexity No Longer Able to Breadboard Systems–Number of chips–Number of components–Length of interconnectsNeed to Simulate and Verify Before Committing to Hardware–Not just logic, but timing01/14/19 ©KJH, 545_a 19Breadth MotivationDifferent Types of Models are Required at Various Development Stages–Logic models–Performance models–Timing models–System models01/14/19 ©KJH, 545_a 20Value of ModelsFormal Expression of System RequirementsCommunicate Actual System Behavior From Designer to UserTest & VerificationFormal Verification of DesignAllow Automatic Synthesis of Design into Hardware01/14/19 ©KJH, 545_a 21SysGen Design to FPGA01/14/19 ©KJH, 545_a 22FPGA Design ProcessCode In VHDL (RTL)Netlist with timingBitstream2. Synthesis and Implementation1. Functional simulation3. Timing simulation4. VerificationVe rificationImplementa t ionSynplify Pro 7.2 and Xilinx ISE 4.1Aldec, Active HDL 5.1Aldec, Active HDL 5.1SLAAC1-V FPGA Board01/14/19 ©KJH, 545_a 23Lengua Franca MotivationNeed a Universal Language for Various Levels of System Design and DesignersReplacement for SchematicsUnambiguous, Formal LanguagePartitions Problem–Design–Simulation and Verification–Synthesis (Implementation)01/14/19 ©KJH, 545_a 24Legacy MotivationStandard for Development of