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MASON ECE 545 - Lecture 4 Introduction to VHDL for Synthesis

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Introduction to VHDL for SynthesisRequired readingRecommended readingSlide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10VHDLGenesis of VHDLA Brief History of VHDLFour versions of VHDLSlide 15VerilogVHDL vs. VerilogSlide 18Slide 19Features of VHDL and VerilogSlide 21Naming and Labeling (1)Naming and Labeling (2)Valid or invalid?Free FormatReadability standards & coding styleCommentsSlide 28Slide 29Example: NAND GateExample VHDL CodeDesign EntityEntity DeclarationEntity declaration – simplified syntaxPort Mode INPort Mode OUTPort Mode OUT (with extra signal)Port Mode BUFFERPort Mode INOUTPort Modes - SummaryArchitecture (Architecture body)Architecture – simplified syntaxEntity Declaration & ArchitectureSlide 44Slide 45Slide 46Library DeclarationsLibrary declarations - syntaxFundamental parts of a libraryLibrariesSlide 51STD_LOGICBIT versus STD_LOGICSTD_LOGIC type demystifiedMore on STD_LOGIC Meanings (1)More on STD_LOGIC Meanings (2)Slide 57More on STD_LOGIC Meanings (4)Resolving logic levelsSTD_LOGIC RulesSlide 61SignalsStandard Logic VectorsVectors and ConcatenationFixed Rotation in VHDLFixed Shift in VHDLSlide 67VHDL Design StylesSlide 69Entity xor3_gateDataflow Architecture (xor3_gate)Dataflow DescriptionStructural Architecture in VHDL 87xor2Structural Architecture in VHDL 93Structural DescriptionBehavioral Architecture (xor3 gate)Behavioral Description?George Mason UniversityIntroduction to VHDLfor SynthesisLecture 42Required reading• P. Chu, RTL Hardware Design using VHDLChapter 2, Overview of Hardware Description LanguagesChapter 3, Basic Language Constructs of VHDL3Recommended reading• Wikipedia – The Free On-line Encyclopedia VHDL - http://en.wikipedia.org/wiki/VHDL Verilog - http://en.wikipedia.org/wiki/Verilog4567ECE 448 – FPGA and ASIC Design with VHDL8ECE 448 – FPGA and ASIC Design with VHDL9ECE 448 – FPGA and ASIC Design with VHDL10ECE 448 – FPGA and ASIC Design with VHDLBrief History of VHDL11VHDL•VHDL is a language for describing digital hardware used by industry worldwide•VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language12Genesis of VHDL•Multiple design entry methods and hardware description languages in use•No or limited portability of designs between CAD tools from different vendors•Objective: shortening the time from a design concept to implementation from 18 months to 6 monthsState of art circa 198013A Brief History of VHDL•June 1981: Woods Hole Workshop•July 1983: contract awarded to develop VHDL•Intermetrics•IBM•Texas Instruments•August 1985: VHDL Version 7.2 released•December 1987: VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standard14Four versions of VHDL•Four versions of VHDL:•IEEE-1076 1987•IEEE-1076 1993  most commonly supported by CAD tools•IEEE-1076 2000 (minor changes)•IEEE-1076 2002 (minor changes)15ECE 448 – FPGA and ASIC Design with VHDLVerilog16Verilog•Simpler and syntactically different•C-like•Gateway Design Automation Co., 1985•Gateway acquired by Cadence in 1990•IEEE Standard 1364-1995•Early de facto standard for ASIC programming•Programming language interface to allow connection to non-Verilog code17 VHDL vs. VerilogGovernment DevelopedCommercially DevelopedAda based C basedStrongly Type Cast Mildly Type CastCase-insensitive Case-sensitiveDifficult to learn Easier to LearnMore Powerful Less Powerful18How to learn Verilog by yourself ?19How to learn Verilog by yourself ?20Features of VHDL and Verilog•Technology/vendor independent•Portable•Reusable21ECE 448 – FPGA and ASIC Design with VHDLVHDL Fundamentals22Naming and Labeling (1)•VHDL is case insensitiveExample:Names or labelsdatabusDatabusDataBusDATABUSare all equivalent23Naming and Labeling (2)General rules of thumb (according to VHDL-87)1. All names should start with an alphabet character (a-z or A-Z)2. Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)3. Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -, etc.)4. Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid)5. All names and labels in a given entity and architecture must be unique24Valid or invalid?7segment_displayA87372477424Adder/Subtractor/resetAnd_or_gateAND__OR__NOTKogge-Stone-AdderRipple&Carry_AdderMy adder25Free Format•VHDL is a “free format” language No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way.Example:if (a=b) thenorif (a=b) then orif (a =b) thenare all equivalent26Readability standards & coding styleAdopt readability standards based on one of the the two main textbooks:Chu or Brown/VranesicUse coding style recommended in OpenCores Coding Guidelineslinked from the course web pageStrictly enforced by the lab instructors and myself.Penalty points may be enforced for not followingthese recommendations!!!27Comments•Comments in VHDL are indicated with a “double dash”, i.e., “--”Comment indicator can be placed anywhere in the lineAny text that follows in the same line is treated as a commentCarriage return terminates a commentNo method for commenting a block extending over a couple of linesExamples:-- main subcircuitData_in <= Data_bus; -- reading data from the input FIFO28Comments•Explain Function of Module to Other Designers•Explanatory, Not Just Restatement of Code•Locate Close to Code Described•Put near executable code, not just in a header29ECE 448 – FPGA and ASIC Design with VHDLDesign Entity30Example: NAND Gatea b z0 0 10 1 11 0 11 1 0abz31Example VHDL Code•3 sections to a piece of VHDL code•File extension for a VHDL file is .vhd•Name of the file should be the same as the entity name (nand_gate.vhd) [OpenCores Coding Guidelines]LIBRARY DECLARATIONENTITY DECLARATIONARCHITECTURE BODYLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY nand_gate ISPORT( a : IN STD_LOGIC;b : IN STD_LOGIC; z : OUT STD_LOGIC);END nand_gate;ARCHITECTURE model OF nand_gate ISBEGINz <= a NAND b;END model;32Design Entity - most basic building block of a design.One entity can have many different architectures.entity declarationarchitecture 1architecture 2architecture 3design entityDesign Entity33ENTITY nand_gate ISPORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC );END nand_gate;Reserved wordsEntity namePort


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MASON ECE 545 - Lecture 4 Introduction to VHDL for Synthesis

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