Survival Guide for synopsys design analyzer: First step is to create a folder in cpe02 where you have to have the folders as vhdl, db, scripts, log, reports. Out of all these folders folder named as vhdl will have all the vhdl source files, scripts folder will have the script(s) and the remaining folders will be empty before you start synthesis. 1. In the search path, library is specified as tcb013ghp_200a, this is for 130 nm library. For 90 nm library the corresponding is tcbn90g_121a. 2. In link library it is tcb013ghptc.db 130 nm and tcbn90gtc.db for 90 nm. 3. In target library it is tcb013ghptc.db 130 nm and tcbn90gtc.db for 90 nm. 4. In symbol library it is tcb013ghp.sdb 130 nm and tcbn90g.sdb for 90 nm. 5. src_directory is the location where you have all your vhdl files. 6. report_directory is the location where the tool writes all report files. 7. db_directory is the location where tool writes all db files and netlist. 8. read_file is used to read the packages you have, if you have any packages in your design replace “components.vhd” with the corresponding package(s) name in your design. 9. blocks = {}, here you need to enter the names of all the blocks you have in your design starting from the bottom level unit and the last block will be your top level (entity of the main program). 10. create_clock -period 13 clk. In this statement clk is the name of the clock, if you have any other name for clock you have to replace clk with the same name. set_clock_latency 0.1 find (clock, "clk") set_clock_transition 0.01 find (clock, "clk") set_clock_uncertainty -setup 0.1 find (clock, "clk") set_clock_uncertainty -hold 0.1 find (clock, "clk") set_input_delay 1.0 -clock clk -max all_inputs() set_output_delay -max 1.0 -clock clk all_outputs() 11. For all the above statements “clk” should be replaced with the name you changed in step10 (if you change). vhdlout_architecture_name = "sort_syn" write -f db -hierarchy -output db_directory + "exam1.db" write -f vhdl -hierarchy -output db_directory + "exam1_syn.vhd" report -area > report_directory + "exam1.report_area" report -timing -all > report_directory + "exam1.report_timing" 12.For the above part you can change the names, so the resulting files from the tool will be named accordingly. Now you are ready to start design analyzer 1. Once you logon to cpe02, go to the directory where you have all your directories (vhdl, db, scripts, log, reports). 2. Go to the log directory using cd log command. 3. Invoke the design analyzer using design_analyzer & command.4. Once the design analyzer is opened, from the toolbar click on Setup and chooses Command Window. This is useful when you want to know the status of synthesis (which command of the script is currently being executed by the tool). 5. After you opened the Command Window ,once again go to the Setup and click on Execute Script. It opens a box where you have to select your script file to be executed. Currently you are in log folder and you will not be able to see any of your script files as they are placed in scripts folder. Go up one directory and click on the scripts folder and select the script to be executed. 6. Once the synthesis is finished you will have db file and vhdl netlist in your db folder and timing and area reports in reports folder. 7. This db file will be used as an input for primetime for static timing analysis and vhdl netlist is an input to formality for formal
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