Timing of digital systemsWhat is an FPGA Chip ?CLB StructureCLB SliceLUT (Look-Up Table) FunctionalityDesign process (1)Design process (2)Slide 8Slide 9Synthesis ToolsFeatures of synthesis toolsTiming report after synthesisImplementationSlide 14Slide 15Slide 16Slide 17Map report headerMap reportPlace & route reportPost layout timing reportSlide 22Timing Characteristics of Combinational CircuitsTiming Characteristics of Combinational Circuits (2)Timing Characteristics of Combinational Circuits (3)Timing Characteristics of Combinational Circuits (4)Timing Characteristics of Sequential Circuits (1)Timing Characteristics of Sequential Circuits (2)Critical Path (1)Critical Path (2)Slide 31Clock JitterClock SkewClock skewH-clock tree used to minimize clock skewDealing With Clock ProblemsBasic I/O Block StructureIOB FunctionalitySlide 39Timing vs. functional simulationSDF fileNetlist from the synthesis toolSlide 43Slide 44Slide 45Slide 46Slide 47Slide 48Slide 49Slide 50Slide 51Speed optimization methods (1)Speed optimization methods (2)ECE 545 – Introduction to VHDL George Mason UniversityTiming of digital systemsECE 545Lecture 9ECE 545 – Introduction to VHDL 2Source: [Brown99]What is an FPGA Chip ?•Field Programmable Gate Array•A chip that can be configured by user to implement different digital hardware•Configurable Logic Blocks and Programmable Switch Matrices•Bitstream to configure: function of each block & the interconnection between logic blocksI/O BlockI/O BlockI/O BlockI/O BlockECE 545 – Introduction to VHDL 3CLB StructureECE 545 – Introduction to VHDL 4COUTDQCKSRECDQCKRECOG4G3G2G1Look-UpTableCarry&ControlLogicOYBYF4F3F2F1XBXLook-UpTableF5INBYSRSCarry&ControlLogicCINCLKCESLICECLB SliceECE 545 – Introduction to VHDL 5LUT (Look-Up Table) Functionality•Look-Up tables are primary elements for logic implementation•Each LUT can implement any function of 4 inputsx1x2x3x4yx1x2yLUTx1x2x3x4y0x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y01000101010011000x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y1111111111110000x1x2x3x4yx1x2x3x4yx1x2yx1x2yLUTx1x2x3x4y0x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y01000101010011000x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y01000101010011000x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y11111111111100000x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y1111111111110000ECE 545 – Introduction to VHDL 6Design process (1)Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..Library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; );end AES_core;SpecificationVHDL description (Your VHDL Source Files)Functional simulationPost-synthesis simulationSynthesisECE 545 – Introduction to VHDL 7Design process (2)Implementation(Mapping, Placing & Routing)ConfigurationTiming simulationOn chip testingECE 545 – Introduction to VHDL 8Design Process control from Active-HDLECE 545 – Introduction to VHDL 9architecture MLU_DATAFLOW of MLU issignal A1:STD_LOGIC;signal B1:STD_LOGIC;signal Y1:STD_LOGIC;signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;beginA1<=A when (NEG_A='0') elsenot A;B1<=B when (NEG_B='0') elsenot B;Y<=Y1 when (NEG_Y='0') elsenot Y1;MUX_0<=A1 and B1;MUX_1<=A1 or B1;MUX_2<=A1 xor B1;MUX_3<=A1 xnor B1;with (L1 & L0) selectY1<=MUX_0 when "00",MUX_1 when "01",MUX_2 when "10",MUX_3 when others;end MLU_DATAFLOW;VHDL descriptionCircuit netlistLogic SynthesisECE 545 – Introduction to VHDL 10Synthesis Tools… and othersECE 545 – Introduction to VHDL 11Features of synthesis tools•Interpret RTL code•Produce synthesized circuit netlist in a standard EDIF format•Give preliminary performance estimates•Some can display circuit schematics corresponding to EDIF netlistECE 545 – Introduction to VHDL 12Timing report after synthesisPerformance Summary *******************Worst slack in design: -0.924 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------exam1|clk 85.0 MHz 78.8 MHz 11.765 12.688 -0.924 inferred Inferred_clkgroup_0System 85.0 MHz 86.4 MHz 11.765 11.572 0.193 system default_clkgroup ===========================================================ECE 545 – Introduction to VHDL 13Implementation•After synthesis the entire implementation process is performed by FPGA vendor toolsECE 545 – Introduction to VHDL 14ECE 545 – Introduction to VHDL 15MappingLUT2LUT3LUT4LUT5LUT1FF1FF2LUT0ECE 545 – Introduction to VHDL 16PlacingCLB SLICESFPGAECE 545 – Introduction to VHDL 17RoutingProgrammable ConnectionsFPGAECE 545 – Introduction to VHDL 18Map report headerRelease 7.1.03i Map H.41Xilinx Mapping Report File for Design 'exam1'Design Information------------------Command Line : c:\Xilinx\bin\nt\map.exe -p 2S200FG256-6 -o map.ncd -pr b -k 4-cm area -c 100 -tx off exam1.ngd exam1.pcf Target Device : xc2s200Target Package : fg256Target Speed : -6Mapper Version : spartan2 -- $Revision: 1.26.6.4 $Mapped Date : Wed Nov 02 11:15:15 2005ECE 545 – Introduction to VHDL 19Map reportDesign Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization: Number of Slice Flip Flops: 144 out of 4,704 3% Number of 4 input LUTs: 173 out of 4,704 3%Logic Distribution: Number of occupied Slices: 145 out of 2,352