ECE 545 Project 2 SpecificationSchedule of Projects (1)Schedule of Projects (2)All Projects – Honor Code RulesOptimization CriteriaProject 2 - Platform & toolsSlide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Project Deliverables Task 1Project Deliverables Task 2Project Deliverables Task 3Slide 21Slide 22ECE 545 Project 2SpecificationSchedule of Projects (1)Project 1 RTL design for FPGAs (20 points)Due date: Tuesday, November 22, midnight (firm)Checkpoints: Monday, October 31, noon - execution unit Monday, November 7, noon - control unit Monday, November 14, noon - testbench & verificationProject 2 RTL design for standard-cell ASICs (10 points)Due date: Tuesday, December 6, midnight (firm)Schedule of Projects (2)Project 3 Behavioral modeling (15 points)Due date: Tuesday, December 20, midnight (firm)All Projects – Honor Code Rules•Using somebody’s else code and presenting it as your own is a serious Honor Code violation and may result in an F grade for the entire course.•All students are expected to write and debug their codes individually.•Students are encouraged to help and support each other in all problems related to the–basic understanding of the problem–operation of the CAD tools.Optimization CriteriaMaximum ratioThroughput divided byTotal Circuit Area [CLB slices] Project 1Project 2Throughput divided byTotal Circuit Area [m2]Project 2 - Platform & toolsTarget devices: standard-cell ASICsLibraries: 90 nm TCBN90G TSMC library 130 nm TCB013GHP TSMC libraryTools:VHDL Simulation: Aldec Active HDL or ModelSimVHDL Synthesis: Synopsys Design CompilerAdjust your synthesizable code for Project 1 in such a way that it can be synthesized using Synopsys and TSMC libraries of standard cells.Task 1Prepare a comprehensive testbench capable of verifying the operation of your entire circuitand run it under ModelSim.This testbench should read test vectors from a text file.All values should be stored in the hexadecimal notation.Verify the function of your circuit using this testbench.Task 2Synthesize your code using Synopsysfor at least two sets of the circuit parameters,using the following tools and libraries:1. Synopsys with the 90 nm TCBN90G TSMC library2. Synopsys with the 130 nm TCB013GHP TSMC library3. Synplify Pro using the smallest device of the Xilinx Spartan 2 family capable of holding the largest of the implemented circuits.Use at least one set of parameters recommended in the specification.Analyze, compare, and discuss the obtained netlists.Task 3For all synthesized circuits, determine• maximum clock frequency• maximum throughput• area • ratio: maximum throughput divided by area.Compare, discuss, and explain results obtained forall analyzed cases.Explain the dependence between values ofparameters (such as word size in RC6, or filterrange in the IIR filter) and the area and timingof your circuit.Task 4Optimize your circuit for the maximum throughput to area ratio.Compare, discuss, and explain results before andafter the optimization.Task 5Tips & Hints (1)Each entity and each package should be placedin a different file.The name of each file should be exactly the sameas the name of an entity or package it contains.Arrange entity names in the bottom-up order(the top-most entity at the end of the list)and define this list in your script using the commandblocks = { entity1, entity2, …, entityN}Tips & Hints (2)Use only one clock in your entire design.Use an identical name for the clock signal in all yourentities and packages (including declarationsof components).Use the same clock name in all clock-related commandsof your script, such as create_clock, set_clock_transition, etc.Avoid advanced features, such as:• multiple clocks, • gated clocks, • multicycle paths, • circular feedback loops containing only combinational logic.Although these features are supported by Synopsys,their correct use requires additional knowledgeand experience that are beyond the scope of ECE 545.Tips & Hints (3)Tips & Hints (4)Create a project directory in your main user directory.Create the following subdirectories in the project directory: db, docs, log, reports, scripts, tb, vhdl.Place all your synthesizable source files in the vhdl directory, and your testbench files in the tbdirectory.Place your scripts in the script directory.Define at least the following directories close to thebeginning of your script: src_directory, report_directory, db_directory.Tips & Hints (5)Do not change values of the constraint conditionsspecified using the following script commands:set_clock_latency 0.1 find(clock, "clk")set_clock_transition 0.01 find(clock, "clk")set_clock_uncertainty -setup 0.1 find(clock, "clk")set_clock_uncertainty -hold 0.1 find(clock, "clk")set_load 0 all_outputs()set_input_delay 1.0 -clock clk -max all_inputs()set_output_delay -max 1.0 -clock clk all_outputs()set_wire_load_model -library tcb013ghptc -name "TSMC8K_Fsg_Conservative"You can change a clock name within these commandsif necessary.These constraints are required to be the same for all students.Tips & Hints (6)Change your current directory to your log directory before you execute design_analyzer.After executing your script within design_analyzer,analyze the contents of log files generated in the directory log.These files contain the exact description of warningsand errors generated during synthesis.Please do your best to eliminate all errors andmajority of warnings generated by the scripts and written to the log files.Project DeliverablesTask 1Source codes of all synthesizable files you have developedin order to meet the project specification. Description of any changes you have had to make in these codes in order to a. get your codes synthesized using Synopsys with TSMC libraries, b. eliminate all synthesis errors and minimize the number of synthesis warnings.Source code of the comprehensive testbench capable of verifying the operation of your entire circuit.Input files containing test vectors, and output filescontaining reports from simulation.Short description of the procedure you have usedto generate test vectors.Project DeliverablesTask 2Analysis of differences among netlistsobtained using Synopsys and Synplify Pro.The detailed descriptions of all differences (if any)between source codes synthesizable using Synplify Proand Synopsys.Project DeliverablesTask 3The detailed timing and area results obtained forall