Slide 1Datapath Circuit for the sort operationControl Circuit – Part 1Pseudocode for the sort operationSlide 5Slide 6ECE 545 – Introduction to VHDL 1SortingECE 545 – Introduction to VHDL 2Datapath Circuit for the sort operationE E E E Clock DataInWrInitRin3Rin2Rin1Rin0E E Bin AinDataOutRdABDataImuxBoutBltA1 0 A B 0 1 RDataR0R1R2R30 1 2 3 ABmuxn n n E E E E Clock DataInWrInitRin3Rin2Rin1Rin0E E Bin AinDataOutRdABDataImuxBoutBltA1 0 A B 0 1 RDataR0R1R2R30 1 2 3 ABmuxn n nECE 545 – Introduction to VHDL 3Control Circuit – Part 1L E L E 1 0 1 0 k 2 –= k –1 = LJEJLIEI2-to-4 decoderWrInitWrRAddClock CselIntImux2 C i C j z i z j CmuxRin0 Rin1 Rin2 Rin3 0 2 2 2 2 2 Counter Counter R Q Q R w 0 w 1 Eny 0 y 1 y 2 y 3 2 L E L E 1 0 1 0 k 2 –= k –1 = LJEJLIEI2-to-4 decoderWrInitWrRAddClock CselIntImux2 C i C j z i z j CmuxRin0 Rin1 Rin2 Rin3 0 2 2 2 2 2 Counter Counter R Q Q R w 0 w 1 Eny 0 y 1 y 2 y 3 2ECE 545 – Introduction to VHDL 4Pseudocode for the sort operationfor i = 0 tok 2 doA = R i ; for j = i + 1 tok 1 doB = R j ; ifB < A thenR i = B ; R j = A ; A = R i ; end if ; end for; end for; ––ECE 545 – Introduction to VHDL 5B A < ? C i 0 s 0 1 S1S2Dones Reset A R i C j C i , C i C i 1 + S4S50 1 S3C j C j 1 + B R j R j A R i B A R i C j k 1 –= ? C j C j 1 + C i k 2 –= ? 0 1 0 1 Load registers0 1 S9S7S6S8B A < ? C i 0 s 0 1 S1S2Dones Reset A R i C j C i , C i C i 1 + S4S50 1 S3C j C j 1 + B R j R j A R i B A R i C j k 1 –= ? C j C j 1 + C i k 2 –= ? 0 1 0 1 Load registers0 1 S9S7S6S8ASM chartfor the sort operationECE 545 – Introduction to VHDL 6ASM chartfor the Control Circuit – Part 2Csel 0 = Int 1 = Ain, , Csel 0 = Int 1 = Wr Bout Csel 1 = Int 1 = Wr Aout Bin Csel 1 = Int 1 = s 0 1 S1S2Done s Reset S4S50 1 S31 0 1 S9S7S6S8LI EI Int 0 = Int 1 = Csel 0 = Ain LJ EJ EJBltAEJEI0 1 0 z j z i Csel 0 = Int 1 = Ain, , Csel 0 = Int 1 = Wr Bout Csel 1 = Int 1 = Wr Aout Bin Csel 1 = Int 1 = s 0 1 S1S2Done s Reset S4S50 1 S31 0 1 S9S7S6S8LI EI Int 0 = Int 1 = Csel 0 = Ain LJ EJ EJBltAEJEI0 1 0 z j z
View Full Document
Unlocking...