ECE 545 Lecture 4 Behavioral & Structural Design StylesResourcesSlide 3VHDL Design StylesAnatomy of a ProcessStatement PartWhat is a PROCESS?Execution of statements in a PROCESSPROCESS with a WAIT StatementWAIT FOR vs. WAITPROCESS with a SENSITIVITY LISTSlide 12Generating selected values of one inputGenerating all values of one inputSlide 15Generating periodical signals, such as clocksGenerating one-time signals, such as resetsTypical errorSlide 19Register Transfer Level (RTL) Design DescriptionSlide 21Component Equivalent of a ProcessProcesses in VHDLSlide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41Shift registerShift Register With Parallel LoadSlide 44Slide 45Slide 46Slide 47Slide 48Sequential Statements (1)Slide 50Slide 51Slide 52Slide 53Slide 54Circuit built of medium scale components2-to-1 MultiplexerVHDL code for a 2-to-1 MultiplexerPriority EncoderVHDL code for a Priority Encoder2-to-4 DecoderVHDL code for a 2-to-4 DecoderSlide 62Slide 63Structural description – example (1)Structural description – example (2)Structural description – example (3)Structural description – example (4)Structural description – example (5)Named association connectivityPositional association connectivityStructural description with positional association connectivitySlide 72Package – example (1)Package – example (2)Package – example (3)Package usage (1)Package usage (2)Package usage (3)Slide 79ConstantsConstants - featuresSlide 82Configuration declarationConfiguration specificationSlide 85Mixed Style ModelingSlide 87Slide 88Slide 89Example 1A 4-to-1 MultiplexerStraightforward code for Example 1Slide 93Modified code for Example 1Slide 95Example 2A 2-to-4 binary decoderVHDL code for Example 2 (1)VHDL code for Example 2 (2)Slide 100Example 3: Variable rotator - InterfaceBlock diagramVHDL code for a 16-bit 2-to-1 MultiplexerFixed rotationVHDL code for for a fixed 16-bit rotatorStructural VHDL code for for a variable 16-bit rotator (1)Structural VHDL code for for a variable 16-bit rotator (2)Structural VHDL code for for a variable 16-bit rotator (3)Slide 109Example 4: Iterative circuits: 8-bit comparator8-bit comparator: Truth TableSlide 112Basic building block – Truth Table8-bit comparator - ArchitectureArchitecture without for-generateSlide 116Slide 117N-bit Comparator – Entity declarationN-bit Comparator – ArchitectureN-bit Comparator – InstantiationECE 545 – Introduction to VHDL George Mason UniversityECE 545Lecture 4Behavioral & StructuralDesign StylesECE 545 – Introduction to VHDL 2Resources• Volnei A. Pedroni, Circuit Design with VHDLChapter 6, Sequential Code (sections 6.1-6.4)Chapter 10, Packages and ComponentsChapter 7.1, Constant• Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 4, Registers and Latches Chapter 9, Design PartitioningECE 545 – Introduction to VHDL 3Behavioral Design Stylefor TestbenchesECE 545 – Introduction to VHDL 4VHDL Design StylesComponents andinterconnectsstructuralVHDL Design StylesdataflowConcurrent statementsbehavioral• TestbenchesSequential statementsECE 545 – Introduction to VHDL 5Anatomy of a Process[label:] process [(sensitivity list)] [declaration part]begin statement partend process [label];OPTIONALECE 545 – Introduction to VHDL 6Statement Part•Contains Sequential Statements to be Executed Each Time the Process Is Activated•Analogous to Conventional Programming LanguagesECE 545 – Introduction to VHDL 7•A process can be given a unique name using an optional LABEL•This is followed by the keyword PROCESS•The keyword BEGIN is used to indicate the start of the process•All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important.•A process must end with the keywords END PROCESS.TESTING: process beginTEST_VECTOR<=“00”;wait for 10 ns;TEST_VECTOR<=“01”;wait for 10 ns;TEST_VECTOR<=“10”;wait for 10 ns;TEST_VECTOR<=“11”;wait for 10 ns;end process;•A process is a sequence of instructions referred to as sequential statements.What is a PROCESS?The Keyword PROCESSECE 545 – Introduction to VHDL 8Execution of statements in a PROCESS•The execution of statements continues sequentially till the last statement in the process.•After execution of the last statement, the control is again passed to the beginning of the process. Testing: PROCESS BEGINtest_vector<=“00”;WAIT FOR 10 ns;test_vector<=“01”;WAIT FOR 10 ns;test_vector<=“10”;WAIT FOR 10 ns;test_vector<=“11”;WAIT FOR 10 ns;END PROCESS;Order of executionProgram control is passed to the first statement after BEGINECE 545 – Introduction to VHDL 9PROCESS with a WAIT Statement•The last statement in the PROCESS is a WAIT instead of WAIT FOR 10 ns.•This will cause the PROCESS to suspend indefinitely when the WAIT statement is executed. •This form of WAIT can be used in a process included in a testbench when all possible combinations of inputs have been tested or a non-periodical signal has to be generated.Testing: PROCESSBEGINtest_vector<=“00”;WAIT FOR 10 ns;test_vector<=“01”;WAIT FOR 10 ns;test_vector<=“10”;WAIT FOR 10 ns;test_vector<=“11”;WAIT;END PROCESS;Program execution stops hereOrder of executionECE 545 – Introduction to VHDL 10WAIT FOR vs. WAIT WAIT FOR: waveform will keep repeating itself foreverWAIT : waveform will keep its state after the last wait instruction.01 2 3…01 2 3…ECE 545 – Introduction to VHDL 11PROCESS with a SENSITIVITY LIST•List of signals to which the process is sensitive.•Whenever there is an event on any of the signals in the sensitivity list, the process fires.•Every time the process fires, it will run in its entirety.•WAIT statements are NOT ALLOWED in a processes with SENSITIVITY LIST.label: process (sensitivity list) declaration part begin statement part end process;ECE 545 – Introduction to VHDL 12TestbenchesECE 545 – Introduction to VHDL 13Generating selected values of one inputSIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0);BEGIN .......testing: PROCESS BEGINtest_vector <= "000";WAIT FOR 10 ns;test_vector <= "001";WAIT FOR 10 ns;test_vector <= "010";WAIT FOR 10 ns; test_vector <= "011";WAIT FOR 10 ns;test_vector <= "100";WAIT FOR 10 ns;END PROCESS; ........END behavioral;ECE 545 – Introduction to VHDL 14Generating all values of one inputSIGNAL test_vector : STD_LOGIC_VECTOR(3 downto 0):="0000";BEGIN