Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Levels of design descriptionRegister Transfer Logic (RTL) Design DescriptionSlide 23Slide 24Design process for FPGAs (1)Design process for FPGAs (2)Slide 27Slide 28Slide 29Course web page: http://ece.gmu.edu/courses/ECE545/index.htmECE 545Introduction to VHDLECE web page  Courses  Course web pages  ECE 545Assistant Professor at GMU since Fall 1998Kris GajOffice hours: R, W 7:30-8:30 PM T 5:00-6:00 PMResearch and teaching interests:• cryptography• network security• computer arithmetic• VLSI design and testingContact:Science & Technology II, room 223 [email protected], (703) 993-1575ECE 545Part of:MS in EEMS in CpEDigital Systems DesignMicroprocessor and Embedded SystemsalgorithmicDesign levelregister-transfergatetransistorlayoutdevicesCoursesComputerArithmeticIntroduction to VHDLDigitalIntegratedCircuits PhysicalVLSI Design VLSI Test Concepts VLSI Design AutomationECE545ECE645ECE 586ECE 680ECE681ECE682ECE684MOS Device ElectronicsNew MS CpE Course RequirementsRecommended for students who by the end of Summer 2004 completed FOUR OR LESS graduate courses towards their MS CpE degreeThere are TWO core courses common for all concentration areas:CS 571 Operating Systems– H. Aydin, S. Setia, C. Snow, project, C/C++ or JavaPros:• Prerequisite for many other courses and projects• HLL (High Level Language) refresher• Offered regularly in Fall and SpringECE 548 Sequential Machine Theory– K. Hintz, R. SchneiderPros:• Common theoretical and mathematical foundation used in all concentrations• Offered regularly in Spring• Not a strong prerequisite for any other course; can be taken any time during the curriculum.Core coursesThere are FOUR required courses separate for each concentration areaCriteria of choice:• Logical sequence of four courses giving a strong foundation for a study, research, and professional position in a given concentration area.• All courses will be offered on a regular basis (at least once per year). Substitutions should be allowed only under exceptional circumstances.• At least two courses are ECE courses taught by the Computer Engineering faculty, the remaining two courses are chosen from among the most related courses in the EE, CS, and INFS programs.• Should include projects, and guarantee the required level of difficulty needed to obtain the CpE degree.Required coursesDIGITAL SYSTEMS DESIGNConcentration advisor: Ken Hintz1. ECE 545 Introduction to VHDL – K. Hintz, K. Gaj, project, VHDL, Aldec/ModelSim, Synplicity/Synopsys2. ECE 645 Computer Arithmetic: HW and SW Implementation – K. Gaj, project, VHDL, Aldec/Synplicity/Xilinx and Synopsys3. ECE 586 Digital Integrated Circuits – D. Ioannou4. ECE 681 VLSI Design Automation – K. Kazi, R. Mehler, project, VHDL, ModelSim and SynopsysMICROPROCESSOR AND EMBEDDED SYSTEMSConcentration advisor: Peter Pachowicz1. ECE 511 Microprocessors– P. Pachowicz2. ECE 545 Introduction to VHDL– K. Hintz, K. Gaj, project, VHDL, Aldec/ModelSim, Synplicity/Synopsys3. ECE 611 Advanced Microprocessors– D. Tabak4. ECE 612 Real-Time Embedded Systems– K. HintzNETWORK AND SYSTEM SECURITYConcentration advisor: Kris Gaj1. ECE 542 Computer Network Architectures and Protocols– S.-C. Chang, et al.2. ECE 646 Cryptography and Computer Network Security– K. Gaj – lab, project, C/C++, VHDL, or analytical3. ECE 746 Secure Telecommunication Systems– K. Gaj – lab, project, C/C++, VHDL, or analytical4. INFS 766 Internet Security Protocols – R. SandhuCOMPUTER NETWORKSConcentration advisor: Brian Mark1. ECE 528 Random Processes in ECE– J. Gertler2. ECE 542 Computer Network Architectures and Protocols– S.-C. Chang3. ECE 642 Design and Analysis of Comp. Comm. Networks – B. Mark – programming assignments Matlab/C++/Java4. ECE 742 High Speed Networks– B. Mark – analytical project• Each student can choose 4 elective courses from a list of electives common for all concentration areas.• All elective courses must be approved by the concentration area advisor (in the form of a partial or complete plan of study) prior to registering for these courses.Elective coursesOld MS CpE Course RequirementsRecommended for students who by the end of Summer 2004 completed FIVE OR MORE graduate courses towards their MS CpE degreeDigital Systems DesignECE 545 ECE 586ECE 548 ECE 584ECE 645 ECE 680 ECE 681 ECE 682Core CoursesRequired Courses(replacement requires an approval of the concentration area advisor)Microprocessor and Embedded SystemsECE 511 CS 571CS 540ECE 542 ECE 548ECE 611 ECE 612 ECE 641CS 668Core CoursesRequired Courses(replacement requires an approval of the concentration area advisor)DIGITAL SYSTEMS DESIGN: Ken HintzConcentration Area Advisors(for both old and new degree requirements)COMPUTER NETWORKS: Brian MarkNETWORK AND SYSTEM SECURITY: Kris GajMICROPROCESSOR AND EMBEDDED SYSTEMS: Peter PachowiczECE 545LectureProjects30 % Homework 30 %Midterm exam 20 % in class 20 % take homeMidterm exam 1 2 hours 30 minutes in-lab open-books, open-notes practice exams will be available on the webThursday, October 28thTentative date:Midterm Exam 2 take-home 24 hoursThursday, December 9thTentative date:Project technologiessemi-custom Application Specific Integrated Circuits and Field Programmable Gate ArraysLevels of design descriptionAlgorithmic levelRegister Transfer LevelLogic (gate) levelCircuit (transistor) levelPhysical (layout) levelLevel of description most suitable for synthesisRegister Transfer Logic (RTL) Design Description Combinational Logic Combinational Logic…ClockRegistersLogic SynthesisVHDL code VHDL simulatorLibrary of standard cellsSpeed without routingArea without routingNetlistDesign Process for ASICs (1)Functional verificationPlacing & routingNetlistLibrary of standard cellsArea with routingSpeed with routingLayoutDesign Process (2)Design process for FPGAs (1)Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..Library IEEE;use ieee.std_logic_1164.all;use