Slide 1TopicsCourse EvaluationJan. 10, 2006 ELEC7250: Course Organization 1ELEC 7250 – VLSI Testing (Spring 2006)Place and Time: Broun 235, Tuesday/Thursday, 11:00AM—12:15PMCourse Website: http://www.eng.auburn.edu/~vagrawal/COURSE/E7250_06/course.htmlCatalog data: ELEC 7250. VLSI Testing (3) Lec. 3. Pr., ELEC 6770. Introduction to VLSI testing, test process and automatic test equipment, test economics and product quality, test economics, fault modeling, logic and fault simulation, testability measures, combinational and sequential circuit test generation, memory test, analog test, delay test, IDDQ test, design for testability, built-in self-test, boundary scan, analog test bus, system test and core test.Textbook: Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits, Michael L. Bushnell and Vishwani D. Agrawal, Boston: Springer, 2006 printing (this version has many corrections over the original (2000) and subsequent printings by Kluwer Academic Publishers.)Other references: Listed in Appendix C of the textbook. Coordinator: Vishwani D. Agrawal, James J. Danaher Professor of Electrical and Computer Engineering Prerequisites by topic: 1. Basic switching theory, 2. Basic digital VLSI designJan. 10, 2006 ELEC7250: Course Organization 2Topics•Overview of electronic testing (1 class)•Test process and ATE (1 class)•Test economics (1 class)•Yield Analysis and product quality (1 class)•Fault modeling (1 class) •Logic simulation (1 class)•Fault simulation (1 class)•Testability measures (2 classes)•Combinational ATPG (3 classes)•Sequential ATPG (3 classes)•Memory test (3 classes)•Analog circuit test (3 classes)•Delay test (2 classes)•IDDQ testing (1 class)•Design for testability (3 classes)•Built-in self-test (2 classes)•Boundary scan (2 classes)•Analog test bus (1 class)•System test and core test (2 classes)Jan. 10, 2006 ELEC7250: Course Organization 3Course Evaluation•Homework (1 per week, most weeks) 30%•Term paper (6 pages) 10%•Class presentation (15 minutes) 10%•Final exam 25% •Project
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