Lecture 11 Major Combinational Automatic Test-Pattern Generation AlgorithmsForward ImplicationBackward ImplicationImplication StackImplication Stack after BacktrackObjectives and Backtracing of ATPG AlgorithmBranch-and-Bound SearchD-Algorithm -- Roth IBM (1966)Singular Cover ExampleD-CubeD-Cube Operation of D-IntersectionPrimitive D-Cube of FailureImplication ProcedureBridging Fault CircuitConstruction of Primitive D-Cubes of FailureBridging Fault D-Cubes of FailureGate Function Change D-Cube of FailureD-Algorithm – Top LevelD-Algorithm – D-driveD-Algorithm -- ConsistencyBacktrackCircuit Example 7.1 and Truth TableSingular Cover & D-CubesSteps for Fault d sa0Example 7.2 Fault A sa0Step 2 -- Example 7.2Step 3 -- Example 7.2Step 4 -- Example 7.2Step 5 -- Example 7.2Step 6 -- Example 7.2D-Chain Dies -- Example 7.2Example 7.3 – Fault s sa1Example 7.3 – Step 2 s sa1Slide 34Example 7.3 – Step 3 s sa1Example 7.3 – Fault u sa1Example 7.3 – Step 2 u sa1Slide 38InconsistentExample 7.3 – BacktrackExample 7.3 – Step 3 u sa1Example 7.3 – Step 4 u sa1Slide 43PODEM -- Goel IBM (1981)MotivationPODEM High-Level FlowSlide 47Slide 48Example 7.3 -- Step 3 s sa1Example 7.3 -- Step 4 s sa1Example 7.3 -- Step 5 s sa1Example 7.3 -- Step 6 s sa1Example 7.3 -- Step 7 s sa1Example 7.3 -- Step 8 s sa1Example 7.3 -- Step 9 s sa1Backtrack -- Step 10 s sa1Step 11 -- s sa1Backtrack -- s sa1Step 13 -- s sa1Step 14 -- s sa1Step 15 -- s sa1Slide 62Step 17 -- s sa1Fault Tested -- Step 18 s sa1Backtrace (s, vs) Pseudo-CodeObjective Selection CodePODEM AlgorithmSummaryCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 1Lecture 11Major Combinational Automatic Test-Pattern Generation AlgorithmsLecture 11Major Combinational Automatic Test-Pattern Generation AlgorithmsDefinitionsD-Algorithm (Roth) -- 1966D-cubesBridging faultsLogic gate function change faultsPODEM (Goel) -- 1981X-Path-CheckBacktracingSummaryCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 2Forward ImplicationForward ImplicationResults in logic gate inputs that are significantly labeled so that output is uniquely determinedAND gate forward implication table:Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 3Backward ImplicationBackward ImplicationUnique determination of all gate inputs when the gate output and some of the inputs are givenCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 4Implication StackImplication StackPush-down stack. Records:Each signal set in circuit by ATPG Whether alternate signal value already tried Portion of binary search tree already searchedCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 5Implication Stack after BacktrackImplication Stack after Backtrack01000001111EFBBFF1UnexploredPresent AssignmentSearched and InfeasibleCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 6Objectives and Backtracing of ATPG AlgorithmObjectives and Backtracing of ATPG AlgorithmObjective – desired signal value goal for ATPGGuides it away from infeasible/hard solutionsBacktrace – Determines which primary input and value to set to achieve objectiveUse testability measuresCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 7Branch-and-Bound SearchBranch-and-Bound SearchEfficiently searches binary search treeBranching – At each tree level, selects which input variable to set to what valueBounding – Avoids exploring large tree portions by artificially restricting search decision choicesComplete exploration is impracticalUses heuristicsCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 8D-Algorithm -- Roth IBM(1966)D-Algorithm -- Roth IBM(1966)Fundamental concepts invented:First complete ATPG algorithmD-CubeD-CalculusImplications – forward and backwardImplication stackBacktrackTest Search SpaceCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 9Singular Cover ExampleSingular Cover ExampleMinimal set of logic signal assignments to show essential prime implicants of Karnaugh mapGateAND123InputsA0X1BX01Outputd001GateNOR123Inputsd1X0eX10OutputF001Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 10D-CubeD-CubeCollapsed truth table entry to characterize logicUse Roth’s 5-valued algebraCan change all D’s to D’s and D’s to D’s (do both)AND gate:Rows 1 & 3Reverse inputsAnd two cubesInterchange D and DAD1DD1DB1DDDD1dDDDDDDCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 11D-Cube Operation of D-IntersectionD-Cube Operation of D-Intersection – undefined (same as ) or  – requires inversion of D and DD-intersection: 0 0 = 0 X = X 0 = 0 1 1 = 1 X = X 1 = 1 X X = XD-containment –Cube a containsCube b if b is a subset of a01XDD000111X01XDDDDDD       Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 12Primitive D-Cube of FailurePrimitive D-Cube of FailureModels circuit faults:Stuck-at-0Stuck-at-1Bridging fault (short circuit)Arbitrary change in logic functionAND Output sa0: “1 1 D”AND Output sa1: “0 X D ” “X 0 D ”Wire sa0: “D”Propagation D-cube – models conditions under which fault effect propagates through gateCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 13Implication ProcedureImplication Procedure1. Model fault with appropriate primitive D-cube of failure (PDF)2. Select propagation D-cubes to propagate fault effect to a circuit output (D-drive procedure)3. Select singular cover cubes to justify internal circuit signals (Consistency procedure)Put signal assignments in test cubeRegrettably, cubes are selected very arbitrarily by D-ALGCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 14Bridging Fault CircuitBridging Fault CircuitCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 15Construction of PrimitiveD-Cubes of FailureConstruction of PrimitiveD-Cubes of Failure1. Make cube set 1 when good machine output is 1 and set 0 when good machine output is 02. Make cube set 1 when failing machine output is 1 and 0 when it is 03. Change 1 outputs to 0 and D-intersect each cube with every 0. If intersection works, change output of cube to D4. Change 0 outputs to 1 and D-intersect each cube with every 1. If intersection works, change output of cube to DCopyright 2001, Agrawal & BushnellVLSI Test: