HILLARY GRIMES III – ELEC 7250 TERM PROJECT HillSIM: A Hierarchical Bench Logic Simulator for Zero Delay Combinational Circuits HILLARY GRIMES III, GRADUATE STUDENT, AUBURN UNIVERSITY Abstract This paper presents an overview of HillSIM (Hill-ary's SIM-ulator), which is a logic simulator and verification program for zero-delay combinational circuits. HillSIM requires two input text files: a circuit description in a hierarchial bench format and a simulation input file containing input vectors to be simulated and the expected output responses to compare with simulated reponses. HillSIM provides a means of verifying a circuit’s logic behavior for a set of input stimuli and expected responses. 1. Introduction Logic simulation is used for design verification during the electronic design process of digital circuits (figure 1) [2]. The design process begins with specification, which is a description of the design's behavior and characteristics, including input stimuli and expected responses. Synthesis produces the netlist, which is an interconnection of electronic components that meets the specification. Logic simulation is used to simulate the circuit for the input stimuli provided from specification. By comparing the simulated responses with the expected responses provided by specification, the design is verified. If errors are found from verification, then the netlist is modified, and verification begins again [2]. Figure 1: Basic design process This paper will present a description of HillSIM (Hill-ary's SIM-ulator), which is a logic simulator and verification program for zero-delay combinational circuits with boolean gates using two states (0 and 1). HillSIM accepts a hierarchical bench netlist input for the circuit description, and verifies the circuit's logic behavior with a list of input vectors and expected output responses. Section 2 of this paper will discuss user information for HillSIM, including a description of the hierarchical bench netlist circuit description. Section 3 will describe data structures and algorithms used in implementing HillSIM, and section 5 will discuss the performance of HillSIM on the ISCAS 85 benchmark circuits and a four bit adder circuit. Section 6 will conclude the paper. 2. User Information HillSIM prompts for two required input text files when executed to perform circuit simulation and verification. The first input file contains the circuit description in a hierarchical bench format, and the second input file contains simulation data (inputs and expected outputs). During execution, HillSIM simulates the specified circuit for each input vector in the simulation input file. Circuit verification is done by comparing the outputs obtained via simulation with the expected outputs specified in the simulation input file. If simulation of every vector produces the proper outputs, then HillSIM's output is simply “Circuit Verified”, and the execution time is printed to the screen. If circuit simulation fails for an input vector, then HillSIM's output specifies which vector failed, the primary outputs where errors are observed, and diagnosis information to help the user diagnose the problem. 2.1 Hierarchical Bench Input File The first input file is the circuit description in a hierarchical bench format, in which each block is separated into its own section with a beginning and an endingHILLARY GRIMES III – ELEC 7250 TERM PROJECT statement. Boolean gates supported include NANDs, ANDs, ORs, NORs, NOTs, and BUFFs. The block begins with “BLOCK blockname”, and ends with an “END” statement. When the block is used within a larger block within the hierarchy, the output signals are listed first, then an “=”, followed by the block name and input signals. The input signals and output signals are listed in the same order as they are declared inside the block. For example, we can define an XOR block, then a Half_Adder block using the previously defined XOR: BLOCK XOR INPUT(A) INPUT(B) OUTPUT(Y) X1=NAND(A,B) X2=NAND(X1,A) X3=NAND(X1,B) Y=NAND(X2,X3) END BLOCK Half_Adder INPUT(in_1) INPUT(in_2) OUTPUT(Sum) OUTPUT(Cout) Sum=XOR(in_1, in_2) Cout=AND(in_1, in_2) END In the statement “Sum=XOR(A,B)” inside the Half_Adder block, Sum corresponds to the XOR's “Y” output, and “in_1” and “in_2” correspond to the XOR's “A” and “B” inputs. 2.2 Simulation Input File The second input file specifies a set of input vectors and expected output responses to be used during circuit verification. Each line of this file contains one input vector and one output response separated by a space or tab. For example, if we wanted to simulate the Half_Adder circuit shown above with an exhaustive set of inputs, our simulation input file would contain the following: # Half_Adder Exhaustive Inputs and Expected Outputs: 00 00 01 10 10 10 11 11 Each input (first column) and output (second column) is specified in the same order they are declared inside the Half_Adder block declaration. The third line contains “10 10”, so in_1 = 1, in_2 = 0, Sum = 1 and Cout = 0. 3. Implementation HillSIM is implemented using the C programming language to run in windows under the cygwin environment. Execution begins by reading the hierarchical bench input circuit description and storing the circuit description in memory using the various data structures discussed in the next section. After the circuit is stored in memory, execution then reads the simulation input file line by line. For each line, the circuit is simulated and its outputs are verified. If verification fails, diagnosis information is printed. 3.1 Data Structures In order to represent the circuit in memory, HillSIM uses the following structures for a signal, gate, and block: struct SIGNAL{ int value; int level; char *name; struct SIGNAL *ptrToInput; struct SIGNAL *ptrToOutput; struct SIGNAL *next; }; struct GATE{ int level;