Lecture 19alt IDDQ Testing (Alternative for Lectures 21 and 22)Basic Principle of IDDQ TestingNAND Open Circuit Defect – Floating gateFloating Gate DefectsDelay FaultsWeak FaultsWeak Fault DetectionLeakage FaultLeakage Fault TableIDDQ Vector SelectionHP and Sandia Lab DataFailure Distribution in Hewlett-Packard ChipSematech StudySematech ResultsSematech Conclusions% Functional Failures After 100 Hours Life TestCurrent Limit SettingDifference in HistogramsDelta IDDQ Testing (Thibeault)|IDDQ| and |DIDDQ|Setting ThresholdIDDQ Built-in Current Testing – Maly and NighConceptual BIC SensorSummaryCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 1Lecture 19altIDDQ Testing(Alternative for Lectures 21 and 22)Lecture 19altIDDQ Testing(Alternative for Lectures 21 and 22) Definition Faults detected by IDDQ tests Weak fault Leakage fault Sematech and other studies Delta IDDQ testing Built-in current (BIC) sensor SummaryCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 2Basic Principle of IDDQ TestingBasic Principle of IDDQ TestingMeasure IDDQ current through Vss busCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 3NAND Open Circuit Defect – Floating gateNAND Open Circuit Defect – Floating gateCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 4Floating Gate DefectsFloating Gate DefectsSmall break in logic gate inputs (100 – 200 Angstroms) lets wires couple by electron tunnelingDelay fault and IDDQ faultLarge open results in stuck-at fault – not detectable by IDDQ testIf Vtn < Vfn < VDD - | Vtp | then detectable by IDDQ testCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 5Delay FaultsDelay FaultsMany random CMOS defects cause a timing delay fault, not catastrophic failureSome delay faults detected by IDDQ test – late switching of logic gates keeps IDDQ elevatedDelay faults not detected by IDDQ testResistive via fault in interconnectIncreased transistor threshold voltage faultCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 6Weak FaultsWeak FaultsnFET passes logic 1 as 5 V – VtnpFET passes logic 0 as 0 V + |Vtp|Weak fault – one device in C-switch does not turn onCauses logic value degradation in C-switchCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 7Weak Fault Detection Weak Fault Detection Fault not detected unless I3 = 1Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 8Leakage FaultLeakage FaultLeakage between bulk (B), gate (G), source (S) and drain (D)Leakage fault table for an MOS component:k = number of component I/O pinsn = number of component transistors m = 2k (number of I/O combinations)m x n matrix M represents the tableEach I/O combination is a matrix rowEntry mi j = octal leakage fault information:Flags fBG fBD fBS fSD fGD fGSSub-entry mi j = 1 if leakage fault detectedCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 9Leakage Fault TableLeakage Fault TableCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 10IDDQ Vector SelectionIDDQ Vector SelectionCharacterize each logic component using switch-level simulation – relate input/output logic values & internal states to: leakage fault detectionweak fault sensitization and propagationStore information in leakage and weak fault tablesGenerate complete stuck-at fault testsLogic simulate stuck-at fault tests – use tables to find faults detected by each vector to select vectors for current measurementCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 11Com-panyHPSan-diaReject ratio(%)Without IDDQWith IDDQWithout IDDQWith IDDQNeither16.460.80OnlyFunct.6.360.09OnlyScan6.040.11Both5.800.00Functional Tests5.5620Scan and Functional TestsHP and Sandia Lab DataHP and Sandia Lab DataHP – static CMOS standard cell, 8577 gates, 436 FFSandia Laboratories – 5000 static RAM testsReject ratio (%) for various tests:Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 12Failure Distribution in Hewlett-Packard ChipFailure Distribution in Hewlett-Packard ChipCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 13Sematech StudySematech StudyIBM Graphics controller chip – CMOS ASIC, 166,000 standard cells0.8 m static CMOS, 0.45 m Lines (Lef), 40 to 50 MHz Clock, 3 metal layers, 2 clocksFull boundary scan on chipTests:Scan flush – 25 ns latch-to-latch delay test99.7 % scan-based stuck-at faults (slow 400 ns rate)52 % SAF coverage functional tests (manually created)90 % transition delay fault coverage tests96 % pseudo-stuck-at fault cov. IDDQ TestsCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 14Sematech ResultsSematech ResultsTest process: Wafer Test Package Test Burn-In & Retest Characterize & Failure AnalysisData for devices failing some, but not all, tests.passpassfailfailpass14652passpass60136failfail146334131251passfail718failpassfailpassfailScan-based Stuck-atIDDQ (5 A limit)FunctionalScan-based delayCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 15Sematech ConclusionsSematech ConclusionsHard to find point differentiating good and bad devices for IDDQ & delay testsHigh # passed functional test, failed all othersHigh # passed all tests, failed IDDQ > 5 ALarge # passed stuck-at and functional testsFailed delay & IDDQ testsLarge # failed stuck-at & delay testsPassed IDDQ & functional testsDelay test caught failures in chips at higher temperature burn-in – chips passed at lower temperatureCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 16% Functional Failures After 100 Hours Life Test% Functional Failures After 100 Hours Life TestWork of McEuen at Ford MicroelectronicsCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 17Current Limit SettingCurrent Limit SettingShould try to get it < 1 AHistogram for 32 bit microprocessorCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 18Difference in HistogramsDifference in HistogramsA – test escapes, B – yield lossCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt 19Delta IDDQ Testing (Thibeault)Delta IDDQ Testing (Thibeault)Use derivative of IDDQ at test vector i as current signatureΔIDDQ (i) = IDDQ (i) – IDDQ (i – 1)Leads to a narrower histogramEliminates variation between chips and between wafersSelect decision threshold Δdef to minimize probability of false