ELEC 7250 project -To Generate a Single Test Vector to detect all/most number of faults in a given combinational circuitELEC-7250 Course ProjectTo Generate a Single Test Vector to detect all/most number offaults in a given combinational circuitSubmitted by Arvind RaghuramanAbstract: The aim of this project is to develop a test generation strategy to obtain a singletest vector to test all/most number of faults in a given combinational circuit. Theproblem was addressed from various perspectives and a solution was achieved. The principle idea behind the solution is to generate all possible test vectors foreach fault from an equivalence collapsed fault set for a given combinational circuit.Now by ascertaining the number of repetitions of each unique test vector among thefault depended test vector sets we can obtain the test vector that detects the mostnumber of faults. A generic windows application designed and developed to implementthe above idea and was used to detect a test vector for the C17 benchmark circuit andthe test results obtained are given below.A test vector set compaction strategy has also been proposed and implemented.Circuit under test : c17 benchmark circuitResult : Test Vector " 0110x " detects 5 faultsCompacted test vector set : 6 vectors (fault coverage 95%)Snap shot of the application:ELEC 7250 project -To Generate a Single Test Vector to detect all/most number of faults in a given combinational circuitIntroduction:The objective of this project is to obtain a test vector that could detect all/mostnumber of faults in a given combinational circuit. In order to accomplish this task a benchfile of the given combinational circuit is generated and equivalence fault collapsing isdone to the parent fault list. ATALANTA (An ATPG software for combinational Circuit’s)was used for this purpose.Now in order to obtain the test vector that would detect most/all number of faultsdifferent approaches were investigated. In the initial thought process ideas were takenfrom the paper on “Independence Fault collapsing” (prepared for VDAT05) byDr.Vishwani Agarwal and Alok Doshi. The initial approach was to exploit theconcurrency property of test vectors and perform elimination based on that to obtain thetest vector of interest. But this approach proved to be too complicated and a round aboutway to solve the given problem.The approach implemented in this project in order to solve the given problem is togenerate test vector sets comprising of test vectors, which could identify each of theunique fault’s present in the equivalence collapsed fault set; this can be done usingoptions provided by ATALANTA. A windows based application was developed whichcould take the output file generated by ATALANTA as input, parse the data andimplement the algorithm to obtain the test vector of interest. Design and Implementationof the algorithm has been discussed in detail in this report. This report talks about the design and implementation of the algorithm proposedin the “Analysis and Algorithms” section. The results obtained for the c17 benchmarkELEC 7250 project -To Generate a Single Test Vector to detect all/most number of faults in a given combinational circuitcircuit are presented under the “Results” section. Ideas are presented for suggestedimprovements, using which the strategy proposed could be used for test vectorcompaction under the “Suggested Improvements” section. The “Conclusion” comprisesof Accomplishments, suggested improvements, and lessons learned.Analysis and Algorithms:The steps involved in implementation of this project are given as follows. The given combinational circuit is taken and a bench file is generated in ICAS85format. Equivalence collapsing is done to the parent fault set using ATALANTA. Fault based test vector generation is done using ATALANTA using the commandoption given below.Command: atalanta -A -t <output file> <inputfile.bench>Using this command ATALANTA generates all possible test vectors that candetect each fault present in the equivalence collapsed fault list and streams the data to theoutput file. The format of ATALANTA output is as shown below.Output file from ATALANTA ATPG for C17.bench circuit:* Name of circuit: c17.bench* Primary inputs : 1 2 3 6 7 * Primary outputs: 22 23 * Test patterns and fault free responses:7 /1 1: x00x0 0011->19 /1 1: xx111 x016->23 /1 1: x10x0 11 2: x1100 1123 /0 1: x10xx 11 2: x110x 11 3: x00x1 01 4: x0101 x119 /1 1: x00x1 01 2: x0101 x123 /1 1: x0xx0 x0 2: x0111 x0 3: x111x x06 /1 1: 0110x 1x11 /1 1: 0111x 0x 2: 11110 10 3: 11111 10 4: x0111 x03->11 /1 1: x101x 1x 2: x0011 0111 /0 1: x10xx 1x 2: 0110x 1x 3: 11100 11 4: 11101 11 5: x00x1 01 6: x0101 x12 /1 1: 000xx 0x11->16 /1 1: x111x x016 /0 1: 00xxx 0x 2: 0111x 00 3: 100xx 0x 4: 101x0 10 5: 10111 10 6: 1111x 1016 /1 1: 010xx 1x 2: 0110x 1x 3: 110xx 1x 4: 11100 113 /1 1: 100xx 0x3 /0 1: 101xx 1x1 /1 1: 001xx 0x3->10 /1 1: 100xx 0x16->22 /1 1: 010xx 11 2: 0110x 11 3: 110xx 1122 /0 1: 1x1xx 1x 2: 110xx 11 3: 010xx 11 4: 0110x 1110 /1 1: 101xx 1x 2: 1111x 1022 /1 1: 00xxx 0x 2: 0111x 00 3: 100xx 0xELEC 7250 project -To Generate a Single Test Vector to detect all/most number of faults in a given combinational circuit The output file generated by ATALANTA is given as input to the windowsapplication to obtain the test vector of interest. The Algorithm implemented in the software is conceptually explained in thediagram given below and in the flow chart & description that follows.Concept explained:ELEC 7250 project -To Generate a Single Test Vector to detect all/most number of faults in a given combinational circuitCombinational CircuitATALANTAF1 - > (TFn1){TV1,TV4,TV6}SET - Fn {TFn1, TFn2, ....TFnm}F2 - > (TFn2) {TV7, TV8, TV6,TV1}F3- > (TFn3) {TV27, TV5, TV6,TV13}FnFn->TFnmSET - (TFnU){TV1, TV2,TV3……. TVn}AELEC 7250 project -To Generate a Single Test Vector to detect all/most number