AUBURN ELEC 7250 - Making s5378 scan testable

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1Making s5378 scan testablePriyanka SinhaDepartment of Electrical and Computer Engineering, Auburn University200 Broun Hall, [email protected]—The steps to make s5378 scan-testable are presented.Combinational vectors have been generated and converted to scansequences in order to simulate faults in the sequential mode.Trivial implementation details are also mentioned. Atalanta,hope, hitec and proofs were the tools used for testing and faultsimulation. The result of the fault simulation of the combinationaland scan vectors are compared and analysed with respect to theircoverage. The scan sequence was found to have less coverage thanthe combinational vectors due to hard to detect and redundantfaults in the scan circuit itself.I. INTRODUCTIONIn order to test a sequential circuit, the time requiredto stabilize the test with the combinational and sequentialparts together takes a long time. Initialization is a problemfor most sequential cicuits. Purely combinational circuits arefound easier to handle. Hence, decoupling the testing of eacheases the problem.This technique is known as scan design . Itrequired extra hardware such as MUXes to be incorporated.A sequential circuit can be visualized as a bunch of D flipflops whose inputs and outputs are connected to combinationallogic. For a detail of the technique of scan design , please view[1]The given circuit s5378 has 35 inputs, 49 outputs, 179 D-type FF’s and 1775 inverters and 1004 other logic gates. This isan example of a rather large circuit in terms of combinationaland sequential elements. As discussed later, the results showthe practical difficulty of testing this circuit.In this report, Section II presents the history of the ideaof Scan Design as given in [1]. Section III illustrates theprocedure I have taken. Section IV discusses the results theand Section V concludes.II. BACKGROUNDScan design for hardware test was detailed in the 1973 paperby Williams and Angell [2]. Various implementations of theconcept were used in companies like IBM, NEC, and others.Apart from the full-scan method used here, random accessmemory scan and partial scan are also different techniques forscan design. Current research focusses on reducing the areaoverhead and hardware required for scan design.III. ANALYSIS AND ALGORITHMSIn order to scan design, the circuit’s FF are represented asD-FF. The circuit requires to follow 4 rules, i.e.,• Only D-type master-slave FFs should be used• At least one primary input pin must be available for test.• All FF clocks must be controllable from primary inputs• Clocks must not feed data inputs of FFsIf the circuit does not follow some of the above rules,techniques for converting the circuit to follow them exist. Inorder to make the s5378 scan testable, I taken the followingsteps• From the directories /opt/atalanta/iscas89/ I have takenthe bench file of the s5378 containing only the combi-national logic and all the inputs to it turned to pseudo-primary-inputs and outputs going to the flip flops aspseudo-primary-outputs. The pseudo-primary-outputs go-ing to more than one FF have been considered as bufferedoutputs. This is in file s5378.scan• Using atalanta generate the compact test vectors for thiss5378.scan by first converting it to the format that atalantatakes the file in. It generates 244 test vectors for this partof the circuit with 40 redundant faults.• The scan hardware is then added to the s5378.scan toplace in the scan FF’s using Transform.java and kept ass5378-Pri.bench• The vectors are then parsed and the scan-sequence gener-ated using ScanSequence.java to be kept as s5378-input-scan-sequence• Using hope, the test vectors s5378-scan-sequence aresimulated upon the s5378-Pri.bench.The relevant files are attached in a zip archive.IV. RESULTSThe s5378.bench was simulated using hitec and found totake ages,263.267 cpu seconds, to generate tests with a lot ofbacktracking and quite few aborted faults,1288, as is evidentfrom the log file, s5378.grs. As can be seen from the log file,LOG, the fault simulation for the combinational part usinghope took 0.600 secs and had a coverage of 99.121% with40 faults being redundant and the sequential part took 87.550secs with a fault coverage of 93.344%. The undetected fault listwas obtained by simulating the circuit using Proofs, and the40 redundant faults from the combinational part were found toexist. Most of the other faults were in the scan design part ofthe circuit. I have not diagnosed why there are more undetectedfaults than these.V. CONCLUSIONS AND ACKNOWLEDGEMENTThe scan design shows that indeed the time to generatethe test for the circuit has reduced greatly. Although the scanchain sequence is long, we find that it takes much less time2than without the scan design. I have accomplished the full-scan design of the s5378.bench circuit. Amongst the lessonsthat I have learnt are that converting a given benchmark circuitto full-scan design is a rather easy process and I could see amarked improvement in the testability of such a circuit. Asfurther work, I need to find out comprehensively the reasonfor different coverage. I would like to acknowledge Anand S.Mudlapur’s for his help in understanding Scan Design.REFERENCES[1] Essentials of Electronic Testing for Digital, Memory andMixed-Signal VLSI circuits, M.L. Bushnell and V.D.Agrawal[2] Enhancing Testability of Large-Scale Integrated Circuitsvia Test Points and Additional Logic, M.J.Y Willaims, J.B.Angell, IEEE Trans on Computers , Jan


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