Andrew WhiteBoundary Scan StandardAndrew WhiteAbstract – Boundary scan, also known as IEEE standard 1149.1, is described bythe Test Technology Standards Committee of the IEEE Computer Society as “circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards” [1]. This standard has become widely used intoday’s printed circuit boards (PCBs) to reduce testing time along with cost. In this paper the IEEE 1149.1 standard’s history, reasoning, and implementations will be discussed.I. INTRODUCTIONIn the mid 1980’s the Joint European Test Action Group (JETAG) was formed in Europe and began developing the Boundary Scan Standard. By 1986 JETAG included not only Europe but also North America and was thus renamed JTAG. After a series of proposals for a standardized form of boundary scan, the IEEE Society finally approved one of them in 1988. Due to the acceptance of the standard from JTAG, JTAG became the core of the group that founded the standard.The initial approval of the standard came in February of 1990 followed by almost immediate supplements. As the standard claims, it defines test logic that can be included into the integrated circuit (IC) to provide easy testing of theinterconnections along with the IC itself.The test logic consists of boundary-scan registers, Test Access Port (TAP), and other building blocks.II. PURPOSEIt was in the 1970’s when in-circuit testing (ICT) became known by testing the backs of PCBs with a board of pins. These testing boards covered in pins became known as a bed-of-nails tester. The reason for the name is simply the design of the test board itself because it is truly what it sounds like, a bed of nails. One of the reasons for this type of ICT was used was because of the way PCBs were actually manufactured. At that time, PCB’s were manufactured using a through-hole method in which allthe ICs were manufactured using dual in-line (DIP) packages as depicted belowin Figure 1.Figure 1. DIP.Since this type of packaging allowed the pins to actually go through the PCBs a connection to every chip could be made through the back of the board. Due to this characteristic a bed-of-nails tester could apply and read signals from any connection in the circuit.A lot has changed since the ICT method first began including, but no limited to, PCB manufacturing. One significant change that has made obsolete the bed-of-nails testers is surface-mount technology (SMT). SMT is the current method used for manufacturing PCB’s due to its low board real estate along with its addedAndrew Whitepins. A depiction of an SMT component is shown below in Figure 2.Figure 2. Ball Grid Array showing SMTDue to these SMT components a new ICT method is being used known as boundary scan.There are two major modes of operation that boundary scan provides: non-invasive and pin-permission. The non-invasive mode activities do not affect the normal behavior of the IC and it is the mode in which the standard requires the ICs to power-up. In this mode, the standard gives resources that are completely independent of the system logic of the chip. These resourcesare what allow the users to asynchronously communicate with the chip through serial communication. The pin-permission modes completely disrupt the normal behavior of the IC and are used for testing the system interconnects separately from the components. In addition, it also allows testing of the components separately from the interconnects.III. BOUNDARY SCAN ARCHITECTUREA. ConfigurationFigure 3 shown below, which was taken from [2], depicts an IC which complies with the boundary scan standard. The boundary scan architectureadded to the IC is made up of 3 functional blocks shown as the test access port (TAP), a TAP controller, and a set of registers.Figure 3. Schematic of Boundary Scan LogicB. Boundary RegisterThe registers connected serially around the periphery of the chip in the previous figure are known as boundary registers. A picture of these types of registers which can be used for an input or output connection is shown below in Figure 4.Figure 4. Boundary Scan Register CellDepending on the multiplexers, data can be loaded into the register through eitherthe “parallel in” line or through the “shift in” line. The second flip-flop in the above figure which is controlled by the “Update-DR” line is provided to ensure that when signals are driven fromthe register through the “parallel out”Andrew Whiteline that the values are held while new data is shifted into the register using the first flip-flop controlled by the “Clock-DR” signal. The instruction register shown in Figure 3 is provided to enables various operation modes of the test hardware. This register is required by the standard and it permits specific commands to be shifted in to select a particular register and/or a certain test function. Three instruction modes are mandatory from the standard while some are optional or even user-defined. The instruction register has certain constraints such as it must be at least two bits long and the lasttwo bits must capture a “01” value. The reason for the minimum two bit constraint is so that it allows the ability to supply unique codes for at least every one of the three required instructions. In addition the last bits “01” can be used during a scan of the instruction register to check the connectivity of the scan chain by forcing a bit toggle at each instruction. This allows for the checking of correct connectivity of the board along with pin-pointing any breaks in thescan chain.The Device ID register shown in Figure 3 is used to provide identificationof the particular device.The last register discussed, the bypass register, is used for bypassing theboundary registers in the component. This is particularly useful when all of theboundary registers are chained together into one long shift registers and the length of the registers is chosen to be reduced by not including hardware on components that are not used during the current test.C. Test Access Port (TAP)The TAP is comprised of 5 pins, 4 mandatory and 1 optional, which are necessary for the boundary scan standard. These pins are defined as the test data in (TDI), test data out (TDO), test clock (TCK), test mode select (TMS), and test reset (TRST*) pins. Theasterisk denotes an active-low signal. These pins can be used in conjunction with a simple protocol to communicate with