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AUBURN ELEC 7250 - Dynamic Levelization

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Motivation for This WorkOutlineLogic SimulatorData structure: UsedAlgorithm in detail: FlowchartLogic Simulator: GUIComplexity: Levelized CircuitsWord on computational savingsDynamic Levelization: ComplexityCPU time vs. number of vectors: 4-bit adder circuitCPU time vs. number of gates: ISCAS’85 circuitsDiagnosis: Primitive StageDiagnosis: Fault DictionaryAlgorithmAlgorithm-ContinuedStuck-at Fault Generator: ATALANTABridge Fault Simulator: AUSIMBacktracing approach: Wrong net connectionComplexity of DiagnosisSimulation & DiscussionConclusionsReferencesThank You . . .20 April 2006 VLSI Testing-Final Project Presentation 1A Robust Logic Simulator Using A Robust Logic Simulator Using Dynamic LevelizationDynamic LevelizationKasi L. K. AnbumonyDept. of Electrical EngineeringAuburn University, AL – 36849 USA20 April 2006 VLSI Testing-Final Project Presentation 2Motivation for This Work• Logic simulator to verify combinational circuits in bench circuit description language.• Logic simulator to handle unlevelized netlists. • Logic simulator to handle hierarchical netlists. • Using Logic simulator as Fault simulator with the help of combinational ATPG & AUSIM.• Gaining popularity to simulate, verify the functionality and diagnose design faults in netlists.20 April 2006 VLSI Testing-Final Project Presentation 3Outline• Definition• Data structure & Algorithm• Complexity• Dynamic Levelization• Results for Logic Simulator• Diagnosis• Fault Dictionary• Algorithm• Atalanta & AUSIM• Simulation & Discussion• Conclusions20 April 2006 VLSI Testing-Final Project Presentation 4Logic Simulator• True value simulator that computes the responses for a given stimuli• Used for design verification• Supports AND, OR, NOT, BUFF, NAND, NOR, XOR, XNOR for any number of fan-ins• Two methods have been tried to optimize the CPU time20 April 2006 VLSI Testing-Final Project Presentation 5Data structure: UsedDynamically growing array with each net having two properties: name and their logic valuenetnamenetvalue20 April 2006 VLSI Testing-Final Project Presentation 6Algorithm in detail: FlowchartStartRead the input andoutput netnamesnetnameI+netnameOAssign values to input netsnetvalueIInputs are assigned logical values(2^N)while! (EOF(*.bench))Input netsofgiven gate==netnameI?Gate evaluated and output netadded to netnameI and netvalueIStore the unfinished netsin an arrayrepeat until EOFAll Inputs havenetvalueIdefined?AND,OR,NAND,NOR-Any fanincontrol value?StopIs unfinishedempty?YesYes NoYesNoYesNoMethod 1Method 2Dynamic Levelization20 April 2006 VLSI Testing-Final Project Presentation 7Logic Simulator: GUI20 April 2006 VLSI Testing-Final Project Presentation 8Complexity: Levelized Circuits• Method 1: If the netlist is levelized with n gates and an average fanin of each gate is k, then complexity is given by O(kn)• Method 2: If one of the fanin’s of a logic gate is a control value (i.e.) for an AND gate it is 0, then we need not wait for other fanin’s for that gate to get stabilized. Saving by a factor of say “k1”. Other gates: OR,NOR,NAND.8765432187654321:)()()()()1()1()1()1(nnnnnnnnnNotenOnOknOknOkknOkknOkknOkknOnotbuffxnorxorornorandnand+++++++=+++++++=20 April 2006 VLSI Testing-Final Project Presentation 9Word on computational savings– 3 out of 4 case, I can apply Method 2 and can get some saving. So I can multiply a weight of ¾ for a saving of – While remaining ¼ will have a complexity of Oand(kn2 (0.25))A B Y=A.B000010100111)1)75.0((2kknOand20 April 2006 VLSI Testing-Final Project Presentation 10Dynamic Levelization: Complexity))()()()(.()()()()()()(3456234561kOkOkOkOMkOkOkOkOkOkO+++++++++=Level 1 nodeLevel 6 nodeLevel 5 nodeLevel 4 nodeLevel 3 nodeLevel 2 node• Where M is the number of traversals on the unsolved nodes to get the final response.• On the right is the worst case depiction with M=(O6(k) + (O6(k) +O5(k))+(O6(k) +O5(k)+O4(k))) + (O6(k) +O5(k)+O4(k)+O3(k) )+ (O6(k) +O5(k)+O4(k) )+ (O6(k) +O5(k)) + (O6(k) )= 7O6(k) +5O5(k)+3O4(k)+1O3(k)20 April 2006 VLSI Testing-Final Project Presentation 11CPU time vs. number of vectors:4-bit adder circuitMATLAB Version: 7.0.4.365 (R14) Service Pack 2Machine: Intel ® Celeron ™ CPU 1.19 GHz with 384 MB RAM20 April 2006 VLSI Testing-Final Project Presentation 12CPU time vs. number of gates: ISCAS’85 circuitsSimulated for 1000 random vectorsProgrammer’s efficiency20 April 2006 VLSI Testing-Final Project Presentation 13Diagnosis: Primitive StageDevice after fabricatedINPUTS OUTPUTS20 April 2006 VLSI Testing-Final Project Presentation 14Diagnosis: Fault DictionaryFault Test syndrome t1t2 t3 t4No faulta0, b0, d0a1b1c0c1, d1, e1e00010010000010100010100100001a0: Line a stuck-at-0ti= 0, if Ti passes= 1, if Ti fails20 April 2006 VLSI Testing-Final Project Presentation 15Algorithm• Creation of fault dictionary for the specific circuit exhaustively for all stuck-at faults and bridge faults • Compare the good circuit and faulty circuit response to generate a signature for all test vectors listed in “fault dictionary”netname_good[] compare with netname_fault[]netvalue_good[] compare with netvalue_fault[]• Compare the signature with the signatures in the fault dictionary• Any match, then higher probability of fault existing of that type or other faults close to that nets20 April 2006 VLSI Testing-Final Project Presentation 16Algorithm-Continued• Update the fault list dictionary, if any new faults found for the same signature • Use minimum hamming distance to find a closer fault, if no signature match and verify those nets for possible faults20 April 2006 VLSI Testing-Final Project Presentation 17Stuck-at Fault Generator: ATALANTA• Use atalanta in diagnostic mode• Command: atalanta –D 1 *.bench• Check *.test for the stuck-at fault and the vector detecting it20 April 2006 VLSI Testing-Final Project Presentation 18Bridge Fault Simulator: AUSIM• Generate random vector patterns and store it *.vec• Convert bench to asl file format• Generate *.lib and *.ctrl file• *.ctrl file contents • ausim *.ctrl• Check *.det file default <filename>procauditsimul8bftgenbftsim20 April 2006 VLSI Testing-Final Project Presentation 19Backtracing approach: Wrong net connection0100101(0)20 April 2006 VLSI Testing-Final Project Presentation 20Complexity of Diagnosis(1) Complexity of Atalanta O(n2)(2) Complexity of AUSIM O(n2) [1](3) Complexity of backtracing is similar to PODEM


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