Lecture 31 System Test (Lecture 22alt in the Alternative Sequence)A System and Its TestingSystem Test ApplicationsFunctional TestGate-Level DiagnosisGate Replacement FaultBridging FaultFault DictionaryDiagnosis with DictionaryDiagnostic TreeSystem Test: A DFT ProblemConventional Test: In-Circuit Test (ICT)PCB vs. SOCCore-Based DesignPartitioning for TestTest-Wrapper for a CoreA Test-WrapperOverhead of Test AccessOverhead EstimateDFT Architecture for SOCDFT ComponentsSummaryCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt 1Lecture 31System Test(Lecture 22alt in the Alternative Sequence)Lecture 31System Test(Lecture 22alt in the Alternative Sequence)DefinitionFunctional testDiagnostic testFault dictionaryDiagnostic treeSystem design-for-testability (DFT) architectureSystem partitioningCore test-wrapperDFT overheadSummaryCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt 2A System and Its TestingA System and Its TestingA system is an organization of components (hardware/software parts and subsystems) with capability to perform useful functions.Functional test verifies integrity of system:Checks for presence and sanity of subsystemsChecks for system specificationsExecutes selected (critical) functionsDiagnostic test isolates faulty part:For field maintenance isolates lowest replaceable unit (LRU), e.g., a board, disc drive, or I/O subsystemFor shop repair isolates shop replaceable unit (SRU), e.g., a faulty chip on a boardDiagnostic resolution is the number of suspected faulty units identified by test; fewer suspects mean higher resolutionCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt 3System Test ApplicationsSystem Test ApplicationsAApplication Functional test Diagnostic test ResolutionManufacturing Yes LRU, SRUMaintenance YesField repair LRUShop repair SRULRU: Lowest replaceable unitSRU: Shop replaceable unitCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt 4Functional TestFunctional TestAll or selected (critical) operations executed with non-exhaustive data.Tests are a subset of design verification tests (test-benches).Software test metrics used: statement, branch and path coverages; provide low (~70%) structural hardware fault coverage.Examples:Microprocessor test – all instructions with random data (David, 1998).Instruction-set fault model – wrong instruction is executed (Thatte and Abraham, IEEETC-1980).Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt 5Gate-Level DiagnosisGate-Level DiagnosisedabcT3T1T2T4abcStuck-at fault tests:T1 = 010T2 = 011T3 = 100T4 = 110Logic circuitKarnaugh map(shaded squares are true outputs)Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt 6Gate Replacement FaultGate Replacement FaultedabcT3T1T2T4abcStuck-at fault tests:T1 = 010 (pass)T2 = 011 (fail)T3 = 100 (pass)T4 = 110 (fail)Faulty circuit(OR replaced by AND)Karnaugh map(faulty output:red sqaure is 1 output)Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt 7Bridging FaultBridging FaultedabcT3T1T2T4abcStuck-at fault tests:T1 = 010 (pass)T2 = 011 (pass)T3 = 100 (fail)T4 = 110 (pass)Faulty circuit(OR bridge: a, c)Karnaugh map(red squares are faulty 1 outputs)a+ca+cCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt 8 Fault Test syndrome t1 t2 t3 t4 No fault a0, b0, d0 a1 b1 c0 c1, d1, e1 e0 Fault DictionaryFault Dictionary0010010000010100010100100001a0 : Line a stuck- at-0ti = 0, if Ti passes = 1, if Ti failsCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt 9Diagnosis with DictionaryDiagnosis with Dictionary Fault Test syndrome Diagnosis t1 t2 t3 t4 OR AND 0 1 0 1 e0OR-bridge (a,c) 0 0 1 0 b1 OR NOR 1 1 1 1 c1, d1, e1, e0Dictionary look-up with minimum Hamming distanceCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt 10Diagnostic TreeDiagnostic TreeT4T1T2T3No faultfoundT3T2b1a1c1, d1, e1a0, b0, d0e0c0Pass: t4=0Fail: t4=1a0, b0, d0, e0a1, c1, d1, e1OR ANDOR bridge(a,c)OR NORCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt 11System Test: A DFT ProblemSystem Test: A DFT ProblemGiven the changing scenario in VLSI:Mixed-signal circuitsSystem-on-a-chipMulti-chip modulesIntellectual property (IP) coresPrepare the engineer for designing testable, i.e., manufacturable, VLSI systems.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt 12Conventional Test:In-Circuit Test (ICT)Conventional Test:In-Circuit Test (ICT)A bed-of-nails fixture provides direct access to each chip on the board.Advantages: Thorough test for devices; good interconnect test.Limitations:Works best when analog and digital functions are implemented on separate chips.Devices must be designed for backdriving protection.Not applicable to system-on-a-chip (SOC).Disadvantages:High cost and inflexibility of test fixture.System test must check for timing.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt 13PCB vs. SOCPCB vs. SOCTested partsIn-circuit test (ICT)Easy test accessBulkySlowHigh assembly costHigh reliabilityFast interconnectsLow costUntested coresNo internal test accessMixed-signal devicesPCB SOCCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt 14Core-Based DesignCore-Based DesignCores are predesigned and verified but untested blocks:Soft core (synthesizable RTL)Firm core (gate-level netlist)Hard core (non-modifiable layout, often called legacy core)Core is the intellectual property of vendor (internal details not available to user.)Core-vendor supplied tests must be applied to embedded cores.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt 15Partitioning for TestPartitioning for TestPartition according to test methodology:Logic blocksMemory blocksAnalog blocksProvide test access:Boundary scanAnalog test busProvide test-wrappers (also called collars) for cores.Copyright 2001, Agrawal & BushnellVLSI Test: