Abstract: In this paper, failing circuits are analyzed and a multiple-fault diagnosis approach is proposed. An incremental simulation-based approach is used to diagnose failures one at a time. Furthermore, to improve the diagnosability, a failing-primary-output partitioning algorithm is proposed. Experimental results show that this approach has approximately linear time complexity, and it achieves high diagnosability and resolution. The diagnosis time is within minutes for real industrial chips that failed because of multiple faults.1.INTRODUCTIONThe purpose of fault diagnosis is to determine the cause of failure in a manufactured, faulty chip. A good diagnostic tool should effectively assist a designer in quickly and accurately locating the reason for failure. Most of the studies on failure analysis have assumed a single defect. However, for present technologies and chip sizes, this assumption may not be true. Multiple defects on a failing chip often better reflect the reality. It is also possible that certain single-location defects behave as multiple faults. Defects of this kind are bridging defects which affect two fault locations, or via defects which may affect multiple branches and which can be modeled as multiple faults at those branches. Diagnostic algorithms can be quantified by several measures. Resolution of an algorithm is measured as a ratio of true faults and the total number of reported candidates. Diagnosability of an algorithm is a measure reflecting the percentage of defects which can be correctly identified.The existing diagnosis algorithms can be divided into two main classes. The first one applies the cause-effect principle. The second one traces the effect-cause dependencies. The former methods build the simulation response database for the modeled faults and compare this database with the observed failure responses to determine the probable cause of the failure. This method is sometimes referred to as the fault dictionary method [2]. For the assumed fault model, whose defect behavior is similar to the modeled fault behavior, this method can give a very good resolution. Otherwise the resolution may be drastically reduced. However, because this method requires a huge fault behavior database, it may have difficulty with large designs. The effect-cause-based algorithms analyze the actual responses and determine which fault(s) might have caused the observed failure effect. This class of methods does not build the fault-response database. They trace backward from each primary output to determine the error-propagation paths for all possible fault candidates. Compared with the cause-effect methods, effect-cause techniques are more memory-efficient and can cope with larger designs.In this paper an incremental approach based on multiple-fault simulation for combinational and full-scan sequential circuits is proposed. This technique requires information concerning only a few failing patterns (typically only 30 to 50), to accurately diagnose the given chip failure responses. Utilization of the Detection Pattern Set and Failing-PO Partition algorithm can significantly help to avoid the inherent exponential time-complexity problem in multiple-fault diagnosis. A diagnostic framework which can handle any specific fault model and invoke any diagnostic algorithm is also developed [7].2.FAILING PATTERN ANALYSIS [6]Suppose that T is a test set and f is a fault. Those patterns in T that can detect f will form the detection pattern set of the fault f. Any single-fault-based diagnostic algorithm uses single fault simulation behavior to match the observed failure responses to the given test patterns. However, in reality, a pattern may activate multiple faults and create a multiple fault behavior.For the purpose of explanation, let us assume that only two faults exist in the circuit. This analysis can be extended to situations with more than two faults. Each failing pattern p in the given diagnostic test set T is classified into one of the following three types [6]:Type-1: p can activate only one fault and observe its effect. This type of pattern is also defined as a single-location-at-a-time (SLAT) pattern.Type-2: p activates both faults and observes their effects,but those effects are not correlated. We say that the faultshave disjoint behavior on the pattern p.Type-3: p activates both faults and observes their effects,but the faults interact on some primary outputs. The faulty effects may cancel each other out on some POs.An Efficient Method for Multiple Fault DiagnosisKhushboo ShethDepartment of Electrical and Computer Engineering Auburn University, Auburn, ALFig. 1: Failing Pattern TypesMost of the diagnostic algorithms are based on the single-fault assumption. These single-fault-based algorithms rely primarily on the type-1 patterns to perform the analysis and find the fault candidates. Each candidate can fully explain some of the failing patterns. If other faults are present in the circuit, they do not manifest themselves in the type-1 diagnostic test patterns. However, when the fault density increases, the probability decreases that the detection pattern set of every fault in the circuit contains a type-1 pattern. Furthermore, due to limited tester storage space, only very few failing patterns can be stored for future failure analysis. The probability is even lower that the detection pattern set of every fault has a type-1 pattern, which suggests that many faults may not be identified by a single fault-based diagnosis algorithm.Fig. 2: Example of a single-fault assumption limitation.Consider the example in Figure 2 which shows why an algorithm based on a single-fault-assumption may not work. Suppose we have 3 patterns, and pattern P1 is a passing pattern. Applying patterns P2 and P3 we observe some failing POs. The single-fault diagnosis algorithm applied on the failing pattern P3 will result in