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AUBURN ELEC 7250 - lec 17a

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Lecture 17alt Analog Circuit Test (Alternative to Lectures 17, 18, 19 and 30)Analog CircuitsTest ParametersAnalog Test (Traditional)DSP-Based Mixed-Signal TestWaveform Synthesizer © 1987 IEEEWaveform Digitizer © 1987 IEEECircuit SpecificationVoltage Mode OperationOperational/Timing Spec.Operating Range Spec.Test Plan: Hardware SetupTest Program PseudocodeAnalog Fault ModelsBipartite Graph of CircuitMethod of ATPG Using SensitivitiesSensitivityIncremental Sensitivity Matrix of CircuitTolerance Box: Single-Parameter VariationWeighted Bipartite GraphIEEE 1149.4 Standard Analog Test Bus (ATB)Test Bus Interface Circuit (TBIC)Analog Boundary Module (ABM)TBIC Switch ControlsDigital/Analog InterfacesSummaryCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 1Lecture 17altAnalog Circuit Test(Alternative to Lectures 17, 18, 19 and 30)Lecture 17altAnalog Circuit Test(Alternative to Lectures 17, 18, 19 and 30) Analog circuits Analog circuit test methods Specification-based testing Direct measurement DSP-based testing Fault model based testing IEEE 1149.4 analog test bus standard SummaryCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 2Analog CircuitsAnalog CircuitsOperational amplifier (analog)Programmable gain amplifier (mixed-signal)Filters, active and passive (analog)Comparator (mixed-signal)Voltage regulator (analog or mixed-signal)Analog mixer (analog)Analog switches (analog)Analog to digital converter (mixed-signal)Digital to analog converter (mixed-signal)Phase locked loop (PLL) (mixed-signal)Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 3Test ParametersTest ParametersDCContinuityLeakage currentReference voltageImpedanceGainPower supply – sensitivity, common mode rejectionACGain – frequency and phase responseDistortion – harmonic, intermodulation, nonlinearity, crosstalkNoise – SNR, noise figureCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 4FilterAnalog Test (Traditional)Analog Test (Traditional)Analog device under test(DUT)~DCETC.DCRMSPEAKETC.Stimulus ResponseCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 5DSP-Based Mixed-Signal TestDSP-Based Mixed-Signal TestMixed-signal device under test (DUT)A/D RAMRAM D/ASend memoryReceive memoryAnalog AnalogDigital DigitalSynchronizationDigital signal processor (DSP)VectorsVectorsSynthesizer DigitizerCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 6Waveform Synthesizer© 1987 IEEEWaveform Synthesizer© 1987 IEEECopyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 7Waveform Digitizer© 1987 IEEEWaveform Digitizer© 1987 IEEECopyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 8Circuit SpecificationCircuit SpecificationKey Performance Specifications: TLC7524C8-bit Multiplying Digital-to-Analog ConverterResolution 8 BitsLinearity error ½ LSB MaxPower dissipation at VDD = 5 V 5 mW MaxSettling time 100 ns MaxPropagation delay time 80 ns MaxCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 9Voltage Mode OperationVoltage Mode OperationData LatchesVOCSWRR R RR2R 2R 2R 2R 2RDB7(MSB)DB6 DB5 DB0(LSB)GNDRFBOUT1OUT2Data InputsVIREFVO = VI (D/256)VDD = 5 VOUT1 = 2.5 VOUT2 = GND0 1 0 0 011 1Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 10Operational/Timing Spec.Operational/Timing Spec.Parameter Test conditions For VDD = 5 VLinearity error±0.5 LSBGain errorMeasured using the internal feedback resistor. Normal full scale range (FSR) = Vref – 1 LSB±2.5 LSBSettling time to ½ LSB OUT1 load = 100 Ω, Cext = 13 pF, etc.100 nsProp. Delay, digital input to 90% final output current80 nsCSWRDB0-DB7tsu(CS) ≥ 40 nsth(CS) ≥ 0 nstw(WR) ≥ 40 ns tsu(D) ≥ 25 ns th(D) ≥ 10 nsCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 11Operating Range Spec.Operating Range Spec.Supply voltage, VDD-0.3 V to 16.5 VDigital input voltage range -0.3 V to VDD+0.3 VReference voltage, Vref±25 VPeak digital input current 10μAOperating temperature -25ºC to 85ºCStorage temperature -65ºC to 150ºCCase temperature for 10 s 260ºCCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 12Test Plan: Hardware SetupTest Plan: Hardware SetupDACOUT2.5 V+Full-scale codeRLOAD1 kΩ+Vout-VrefD7-D0VM+-Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 13Test Program PseudocodeTest Program Pseudocode dac_full_scale_voltage() { set VI1 = 2.5 V; /* Set the DAC voltage reference to 2.5 V */ start digital pattern = “dac_full_scale”; /* Set DAC output to+full scale (2.5 V) */ connect meter: DAC_OUT /* Connect voltmeter to DAC output */ fsout = read_meter(), /* Read voltage level at DAC_OUT pin */ test fsout; /* Compare the DAC full scale output to data sheet limit */ }Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 14Analog Fault ModelsAnalog Fault ModelsA1First stage gain R2 / R1A2High-pass filter gain R3 and C1fC1High-pass filter cutoff frequency C1A3Low-pass AC voltage gain R4, R5 and C2A4Low-pass DC voltage gain R4 and R5fC2Low-pass filter cutoff frequency C2Op AmpHigh-pass filterLow-pass filter amplifierCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 15Bipartite Graph of CircuitBipartite Graph of CircuitMinimum set of parameters to be observedCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 16Method of ATPG Using SensitivitiesMethod of ATPG Using SensitivitiesCompute analog circuit sensitivities2Construct analog circuit bipartite graphFrom graph, find which O/P parameters (performances) to measure to guarantee maximal coverage of parametric faultsDetermine which O/P parameters are most sensitive to faultsEvaluate test quality, add test points to complete the analog fault coverageN. B. Hamida and B. Kaminska, Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling, ITC-1993Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 17SensitivitySensitivityDifferential (small element variation): S = × =Incremental (large element variation): ρ = ×Tj – performance parameterxi – network elementTjxixi ∂TjTj ∂xiΔTj / TjΔxi / xiΔ xi → 0TjxixiTjΔTjΔxiCopyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 18Incremental Sensitivity Matrix of CircuitIncremental Sensitivity Matrix of Circuit-0.9100000R1100000R200.58-0.91000C100.38-0.89000R3000-0.96-0.970R40000.48-0.97-0.88R5000-0.480-0.91C2A1A2fc1A3A4fc2Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt 19Tolerance


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