Daniel Milton ELEC 7250 VLSI Testing Term Project Report Logic Simulator for Hierarchical BENCH Format The objective for this semester project was to develop a logic simulator that used the BENCH netlist format as an input For added convenience the BENCH input was allowed to have hierarchy in the circuit netlist Hierarchy is beneficial because it removes tedious work required to build a BENCH netlist for circuits that contain repeating sub circuits Noticing that none of the available tools can interpret BENCH with hierarchy this functionality must be created The design flow for this project is as follows develop a BENCH syntax that adds an extension for hierarchy develop a compiler to flatten the netlist and create a simulation table and finally to implement a simulator that applies test vectors to the virtual circuit built from the BENCH netlist To aid in illustrating the hierarchical BENCH format a 4 bit ripple carry adder will be designed using the format Figure 1 a shows the regular BENCH format that can readily be used in CAD tools such as HITEC Figure 1 b depicts the hierarchy BENCH format In this figure the input and output notation is the same however the gate INPUT 1 INPUT 2 INPUT 3 INPUT 6 INPUT 7 OUTPUT 22 OUTPUT 23 10 NAND 1 3 11 NAND 3 6 16 NAND 2 11 18 NAND 11 7 22 NAND 10 16 23 NAND 16 18 instantiations are not component instantiations The USE identifier is used signal the use of INPUT 1 LSB of A INPUT 2 INPUT 3 INPUT 4 MSB of A INPUT 5 LSB of B INPUT 6 INPUT 7 INPUT 8 MSB of B INPUT 14 initial carry in OUTPUT 9 LSB output OUTPUT 10 OUTPUT 11 OUTPUT 12 MSB output OUTPUT 13 Carry USE FA FA1 1 5 14 9 c1 USE FA FA2 2 6 c1 10 c2 USE FA FA3 3 7 c2 11 c3 USE FA FA4 4 8 c3 12 13 a component In general a component is instantiated with the following a b Regular BENCH format Hierarchy BENCH format Figure 1 syntax USE component name component instantation name INPUT OUTPUT NETLIST NETLIST Another restriction with this format is that the component name must correspond to a file with the same name This file will contain a flattened regular BENCH format netlist Note that only one level of components is allowed The component cannot have its own components Now that a hierarchical BENCH format has been defined a BENCH compiler is needed The compiler has two functions to flatten a component based BENCH netlist and to generate a simulation table Flattening the netlist requires the compiler to replace the component instantiations with a copy of the component netlist Obviously there may exist an issue with interconnection naming The compiler must be able to provide a unique naming convention for each component that is flattened The convention used is to concatenate the component instantiation name with the component signal automatically Since no component can have the same name this convention should ensure that each net in the netlist is unique The second function of the compiler is to generate a simulation table for the flattened circuit or for the hierarchical version This table contains the gate or component name type fan in fan out delays and faults Implementing the COMPILER was partitioned into two subtasks correctly parse the BENCH file and generate the simulation table Java was used to implement both functions Java excels quite well at file parsing due to its easy to use string manipulation functions As each line of the file was read in the compiler builds an object called a SIM circuit The SIM circuit is an array of SIM NODEs SIM NODES contain the entirety of the simulation table for a gate or component A visual representation of the Java Classes is given in Figure 2 The classes that begin with COMP are built when a simulation table is created from the non flattened netlist Figure 2 Java Class Diagram Figure 3 depicts the output of the compiler when the flatten option is selected Notice that the signal fFA1 is a generated net The f term came from the BENCH file named FA bench and was concatenated with FA1 the name of the full adder Appendix A contains output information for the simulation tables Figure 3 Flatten BENCH results The final phase of the project required the implementation of a logic simulator that used the hierarchical BENCH format as an input Clearly the previous portions of the project can be used immediately to convert the input file to a data object in memory The simulator is built on top of the compiler in this implantation Once the file has been parsed and a basic data structure built the data structure is then manipulated to bring the data structure to a state that a simulation algorithm can use The following are function calls within the java code that illustrate this manipulation sim analyze sim print sim readyCIR SIM sim genALLVectors sim initPIPO sim cir simulate sim genRANDVectors sim initPIPO sim cir simulate In this code example sim is the SIM circuit object which contains all of the gates in the circuit The analyze function determines the fan in and fan out dependencies between all of the gate nodes The print function generates the simulation table as seen in Appendix A ReadyCIR SIM converts all of the nodes in the circuit to have fan in and fan outs of type SUB NODES Previously the fan ins and fan outs where dynamic array lists that contained the name of the net For simulation purposes a current logic value is also needed and information concerning if this net is a PI or PO in the entire circuit The function genALLVectors generates the entire test vector set for a given size of inputs This vector array is stored in memory Likewise the function genRANDVectors generates 1000 test vectors with a vector width equal to the inputs of the circuit The initPIPO function takes the first test vector from the list and drives it to the inputs of the circuit The logic simulation is completed for all test vectors by calling the cir simulate function This function propagates the PI vales to the PO of the circuit Figure 4 illustrates the class dependencies for the logic simulator implementation Figure 4 Updated Class Diagram for Simulator Figure 5 shows the steps the CIR SIMULATE function completes as it simulates the circuit When a gate s inputs are simulated the output value is recorded and all of the fan ins from the recorded output are updated as well Each time a fanin is updated that gate node is added to a list of nodes that can be simulated Initially all of the PI gates are simulated and the simulation node list grows However if the list already has the