AUBURN ELEC 7250 - BENCH Format (10 pages)

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BENCH Format



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BENCH Format

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Pages:
10
School:
Auburn University
Course:
Elec 7250 - VLSI TESTING (3)

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Daniel Milton ELEC 7250 VLSI Testing Term Project Report Logic Simulator for Hierarchical BENCH Format The objective for this semester project was to develop a logic simulator that used the BENCH netlist format as an input For added convenience the BENCH input was allowed to have hierarchy in the circuit netlist Hierarchy is beneficial because it removes tedious work required to build a BENCH netlist for circuits that contain repeating sub circuits Noticing that none of the available tools can interpret BENCH with hierarchy this functionality must be created The design flow for this project is as follows develop a BENCH syntax that adds an extension for hierarchy develop a compiler to flatten the netlist and create a simulation table and finally to implement a simulator that applies test vectors to the virtual circuit built from the BENCH netlist To aid in illustrating the hierarchical BENCH format a 4 bit ripple carry adder will be designed using the format Figure 1 a shows the regular BENCH format that can readily be used in CAD tools such as HITEC Figure 1 b depicts the hierarchy BENCH format In this figure the input and output notation is the same however the gate INPUT 1 INPUT 2 INPUT 3 INPUT 6 INPUT 7 OUTPUT 22 OUTPUT 23 10 NAND 1 3 11 NAND 3 6 16 NAND 2 11 18 NAND 11 7 22 NAND 10 16 23 NAND 16 18 instantiations are not component instantiations The USE identifier is used signal the use of INPUT 1 LSB of A INPUT 2 INPUT 3 INPUT 4 MSB of A INPUT 5 LSB of B INPUT 6 INPUT 7 INPUT 8 MSB of B INPUT 14 initial carry in OUTPUT 9 LSB output OUTPUT 10 OUTPUT 11 OUTPUT 12 MSB output OUTPUT 13 Carry USE FA FA1 1 5 14 9 c1 USE FA FA2 2 6 c1 10 c2 USE FA FA3 3 7 c2 11 c3 USE FA FA4 4 8 c3 12 13 a component In general a component is instantiated with the following a b Regular BENCH format Hierarchy BENCH format Figure 1 syntax USE component name component instantation name INPUT OUTPUT NETLIST NETLIST Another restriction with this format is that the component name must



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