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AUBURN ELEC 7250 - Combinational ATPG

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Lecture Lecture 9alt 9alt Combinational Combinational ATPG ATPG A A Shortened Shortened version version of of Original Original Lectures Lectures 9 12 9 12 Copyright 2001 Agraw al Bushnell ATPG problem Algorithms Multi valued algebra D algorithm Podem ATPG system Summary Exercise VLSI Test Lecture 9alt 1 ATPG ATPG Problem Problem ATPG Automatic test pattern generation Given A circuit usually at gate level A fault model usually stuck at type Find A set of input vectors to detect all modeled faults Core problem Find a test vector for a given fault Combine the core solution with a fault simulator into an ATPG system Copyright 2001 Agraw al Bushnell VLSI Test Lecture 9alt 2 What What is is a a Test Test Fault activation Fault effect Primary inputs PI X 1 0 0 1 0 1 X X Combinational circuit 1 0 Stuck at 0 fault Copyright 2001 Agraw al Bushnell VLSI Test Lecture 9alt 1 0 Primary outputs PO Path sensitization 3 ATPG ATPG is is a a Search Search Problem Problem Search the input vector space for a test Initialize all signals to unknown X state complete vector space is the playing field Activate the given fault and sensitize a path to a PO narrow down to one or more tests Vector Space Vector Space Circuit X X X X 0 sa1 1 001 Copyright 2001 Agraw al Bushnell Circuit VLSI Test Lecture 9alt sa1 0 1 101 4 Need Need to to Deal Deal With With Two Two Copies Copies of of the the Circuit Circuit Good circuit Same input 0 1 Faulty circuit X X 0 1 sa1 Copyright 2001 Agraw al Bushnell 1 Different outputs X X 0 Alternatively use a multi valued algebra of signal values for both good and faulty circuits Circuit X X 0 1 VLSI Test Lecture 9alt sa1 0 1 5 Multiple Valued Multiple Valued Algebras Algebras Symbol Fault free Faulty Alternative Representation circuit Circuit D D 0 1 X G0 G1 F0 F1 Copyright 2001 Agraw al Bushnell 1 0 0 1 0 0 1 1 X X 0 X 1 X X 0 X 1 1 0 0 1 X 0 1 X X VLSI Test Lecture 9alt 0 1 0 1 X X X 0 1 Roth s Algebra Muth s Additions 6 Function Function of of NAND NAND Gate Gate Input a c b 1 0 1 D Copyright 2001 Agraw al Bushnell c Input b a D 1 0 0 1 X D D 0 1 1 1 1 1 1 1 0 X D D X 1 X X X X D 1 D X D 1 D 1 D X 1 D VLSI Test Lecture 9alt 7 D Algorithm D Algorithm Roth Roth et et al al 1967 1967 D alg D alg II II Use D algebra Activate fault Place a D or D at fault site Do justification forward implication and consistency check for all signals Repeatedly propagate D chain toward POs through a gate Do justification forward implication and consistency check for all signals Backtrack if A conflict occurs or D frontier becomes a null set Stop when D or D at a PO i e test found or If search exhausted without a test then no test possible Copyright 2001 Agraw al Bushnell VLSI Test Lecture 9alt 8 Definitions Definitions Justification Changing inputs of a gate if the present input values do not justify the output value Forward implication Determination of the gate output value which is X according to the input values Consistency check Verifying that the gate output is justifiable from the values of inputs which may have changed since the output was determined D frontier Set of gates whose inputs have a D or D and the output is X Copyright 2001 Agraw al Bushnell VLSI Test Lecture 9alt 9 Definition Definition Singular Singular Cover Cover A singular cover defines the least restrictive inputs for a deterministic output value Used for a b Line justification determine gate inputs for specified output Forward implication determine gate output X X Examples Copyright 2001 Agraw al Bushnell 0 c XX0 110 110 0XX 0X1 0X1 Singular covers a b c SC 1 0 X 1 SC 2 X 0 1 SC 3 1 1 0 VLSI Test Lecture 9alt 10 Definition Definition D Cubes D Cubes D cubes are singular covers with five valued signals Used for D drive propagation of D through gates and forward implication a b Examples X X D c XDX 1DD 1DD 0DX 0D1 0D1 DDX DD1 DD1 Copyright 2001 Agraw al Bushnell D cube a b c D 1 D 1 D D 2 1 D D D 3 1 D D 4 D 1 D D D 5 D D D D 6 D D D D 7 D 0 1 D 8 0 D 1 D 9 D D 1 D 10 D D 1 VLSI Test Lecture 9alt 11 D Intersection D Intersection 0 0 0 1 X D D D 0 1 1 1 X D D D D D D X Copyright 2001 Agraw al Bushnell 1 0 VLSI Test Lecture 9alt Undefined State conflict D 12 An An Example Example XOR XOR a2 a b a1 c1 c b1 f c2 e b2 Find tests for Copyright 2001 Agraw al Bushnell d c sa0 c1 sa0 c2 sa0 VLSI Test Lecture 9alt 13 XOR Test for c sa0 XOR a2 Test for c sa0 a b a1 c1 d c f c2 b1 e b2 Action Operation D frontier 1 Activate fault c 1 or c c1 c2 D d e 2 Justify c 1 XX1 0X1 0X1 a a1 a2 0 d e 3 Forward impl a2 0 0DX 0D1 0D1 d 1 e 4 Forward imp d 1 1XX XXX 1XX no implication possible e 5 D drive c2 e DXX D1D D1D b2 b b1 1 e D f 6 Forward impl b1 1 011 0X1 011 consistency checked f 7 D drive e f 1DX 1DD 1DD f D PO 8 Stop test found Test a b 0 1 f 1 Copyright 2001 Agraw al Bushnell VLSI Test Lecture 9alt 14 Finding Finding Other Other Detected Detected Faults Faults by by the the Generated Generated Test Test Use any fault simulator Serial Deductive Concurrent Other Test Detect A simple fault simulation algorithm Uses true value simulation Uses D algebra for fault analysis Roth et al 1967 Copyright 2001 Agraw al Bushnell VLSI Test Lecture 9alt 15 Test Detect Test Detect XOR XOR Test Test 0 1 0 1 Determine good circuit signal values For each fault Place a D or D at the fault site Perform forward implications Fault is detected if any PO assumes a D or D value D for c1 sa0 a2 a b 0 a1 1 b1 b2 D for c2 sa0 Copyright 2001 Agraw al Bushnell 0DX 0D1 0D1 null D frontier c1 sa0 not detected 1 d c1 1 c f c2 1 D 0 e 1DX 1DD 1DD D at PO D c2 sa0 is detected D1X D1D D1D VLSI Test Lecture 9alt 16 XOR XOR a2Test …


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