Lecture 8 Testability MeasuresWhat are Testability Measures?Testability AnalysisSCOAP MeasuresRange of SCOAP MeasuresCombinational ControllabilityControllability Formulas (Continued)Combinational ObservabilityObservability Formulas (Continued)Comb. ControllabilityControllability Through Level 2Final Combinational ControllabilityCombinational Observability for Level 1Combinational Observabilities for Level 2Final Combinational ObservabilitiesSequential Measures (Comparison)D Flip-Flop EquationsD Flip-Flop Clock and ResetTestability ComputationSequential Example InitializationAfter 1 IterationAfter 2 IterationsAfter 3 IterationsStable Sequential MeasuresFinal Sequential ObservabilitiesTestability Measures are Not ExactSummaryExerciseCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 1Lecture 8Testability MeasuresLecture 8Testability MeasuresDefinitionControllability and observabilitySCOAP measuresCombinational circuitsSequential circuitsSummaryCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 2What are Testability Measures?What are Testability Measures?Approximate measures of:Difficulty of setting internal circuit lines to 0 or 1 from primary inputs.Difficulty of observing internal circuit lines at primary outputs.Applications:Analysis of difficulty of testing internal circuit parts – redesign or add special test hardware.Guidance for algorithms computing test patterns – avoid using hard-to-control lines.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 3Testability AnalysisTestability Analysis Determines testability measures Involves Circuit Topological analysis, but no test vectors (static analysis) and no search algorithm. Linear computational complexity Otherwise, is pointless – might as well use automatic test-pattern generation and calculate: Exact fault coverage Exact test vectorsCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 4SCOAP MeasuresSCOAP MeasuresSCOAP – Sandia Controllability and Observability Analysis ProgramCombinational measures:CC0 – Difficulty of setting circuit line to logic 0CC1 – Difficulty of setting circuit line to logic 1CO – Difficulty of observing a circuit lineSequential measures – analogous:SC0SC1SORef.: L. H. Goldstein, “Controllability/Observability Analysis of Digital Circuits,” IEEE Trans. CAS, vol. CAS-26, no. 9. pp. 685 – 693, Sep. 1979.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 5Range of SCOAP MeasuresRange of SCOAP MeasuresControllabilities – 1 (easiest) to infinity (hardest)Observabilities – 0 (easiest) to infinity (hardest)Combinational measures:Roughly proportional to number of circuit lines that must be set to control or observe given line.Sequential measures:Roughly proportional to number of times flip-flops must be clocked to control or observe given line.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 6Combinational ControllabilityCombinational ControllabilityCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 7Controllability Formulas(Continued)Controllability Formulas(Continued)Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 8Combinational ObservabilityCombinational ObservabilityTo observe a gate input: Observe output and make other input values non-controlling.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 9Observability Formulas(Continued)Observability Formulas(Continued)Fanout stem: Observe through branch with best observability.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 10Comb. ControllabilityComb. ControllabilityCircled numbers give level number. (CC0, CC1)Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 11Controllability Through Level 2Controllability Through Level 2Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 12Final Combinational ControllabilityFinal Combinational ControllabilityCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 13Combinational Observability for Level 1Combinational Observability for Level 1Number in square box is level from primary outputs (POs).(CC0, CC1) COCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 14Combinational Observabilities for Level 2Combinational Observabilities for Level 2Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 15Final Combinational ObservabilitiesFinal Combinational ObservabilitiesCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 16Sequential Measures (Comparison)Sequential Measures (Comparison)CombinationalIncrement CC0, CC1, CO whenever you pass through a gate, either forward or backward.SequentialIncrement SC0, SC1, SO only when you pass through a flip-flop, either forward or backward.BothMust iterate on feedback loops until controllabilities stabilize.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 17D Flip-Flop EquationsD Flip-Flop EquationsAssume a synchronous RESET line.CC1 (Q) = CC1 (D) + CC1 (C) + CC0 (C) + CC0 (RESET)SC1 (Q) = SC1 (D) + SC1 (C) + SC0 (C) + SC0 (RESET) + 1CC0 (Q) = min [CC1 (RESET) + CC1 (C) + CC0 (C), CC0 (D) + CC1 (C) + CC0 (C)]SC0 (Q) is analogousCO (D) = CO (Q) + CC1 (C) + CC0 (C) + CC0 (RESET)SO (D) is analogousCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 18D Flip-Flop Clock and ResetD Flip-Flop Clock and ResetCO (RESET) = CO (Q) + CC1 (Q) + CC1 (RESET) + CC1 (C) + CC0 (C)SO (RESET) is analogousThree ways to observe the clock line:1. Set Q to 1 and clock in a 0 from D2. Set the flip-flop and then reset it3. Reset the flip-flop and clock in a 1 from DCO (C) = min [ CO (Q) + CC1 (Q) + CC0 (D) + CC1 (C) + CC0 (C), CO (Q) + CC1 (Q) + CC1 (RESET) + CC1 (C) + CC0 (C), CO (Q) + CC0 (Q) + CC0 (RESET) + CC1 (D) + CC1 (C) + CC0 (C)]SO (C) is analogousCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 8alt 19Testability ComputationTestability Computation1. For all PIs, CC0 = CC1 = 1 and SC0 = SC1 = 02. For all other nodes, CC0 = CC1 = SC0 = SC1 = ∞3. Go from PIs to POs, using CC and SC equations to get controllabilities -- Iterate on loops until SC stabilizes -- convergence is guaranteed.4. Set CO = SO = 0 for POs, ∞ for all other lines.5. Work from POs to PIs, Use CO, SO, and controllabilities to get observabilities.6. Fanout stem (CO, SO) = min branch (CO, SO)7. If a CC or SC (CO or SO) is ∞ , that node is uncontrollable
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