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AUBURN ELEC 7250 - SEQUENTIAL PARALLEL FAULT SIMULATOR

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ELEC 7250 SEQUENTIAL PARALLEL FAULT SIMULATOR Madhurima Maddela Abstract Fault simulators are used to determine which faults are detected by a test sequence. Designing fault simulators for sequential circuits is much more complicated than for combinational circuits because of the feedback and timing constraints. This report presents an overview of the sequential fault simulators and an at length analysis of two different asynchronous sequential parallel fault simulator models-PROOFS and PARIS which have been further modified to get better performance in the form of HOPE and VISION respectively. The comparison of performances on benchmark circuits shows that with a few exceptions, HOPE proves to be faster than the rest. This paper concentrates on synchronous sequential fault simulators alone.I. INTRODUCTION Logic circuits can be broadly classified as either combinational or sequential logic circuits. In combinational logic, the outputs depend only on the present inputs. But in sequential logic, the outputs are a function of not only the present inputs but of the past inputs as well. In other words, sequential logic has storage (memory) whereas combinational logic does not. Figure 1 shows the block diagram of a sequential circuit. Fig. 1: Block diagram of a sequential circuit Again, sequential circuits can either be synchronous or asynchronous. A clocked sequential logic is termed as synchronous sequential logic. It has a clock signal and all internal memory change at the clock edge. The basic storage element in synchronous sequential logic is a flip-flop. Every operation in the circuit must be completed inside a fixed interval of time between two clock pulses, called a 'clock cycle'. It is simple but has some disadvantages. The clock signal must be distributed to every flip-flop in the circuit, so power is dissipated; even the flip-flops that are doing nothing consume a small amount of power. Also, the maximum possible clock rate is determined by the slowest logic path in the circuit, otherwise known as the critical path. Hence the circuit is only as fast as the critical path. Asynchronous sequential logic is the most general kind of sequential logic, because of its flexibility, but it is also the most difficult kind to design. The basic storage element in asynchronous logic is a latch. Latches can change state at any time, depending on the transitions of other signals which may themselves be produced by other latches. The complexity of asynchronous circuits tends to rise very rapidly as the number of logic gates increases. This paper takes us through different types of sequential fault simulators and discusses four of them in depth---PROOFS, PARIS, VISION and HOPE, in that order. II. FAULT SIMULATION TECHNIQUES With the development of VLSI technologies, test sequences with very high fault coverage have become increasingly important in maintaining acceptable field reject rates. Fault simulators are used to determine which faults are detected by a test sequence. This information not only grades the quality of the test sequence but also speeds up the test generation process. After a test sequence is generated for one target fault by a time-consuming test generator, a fault simulator is usually used for finding other faults that arealso detected. In this manner, the number of faults which need to be targeted by a test generator can be dramatically reduced. Fault simulators are also used to find test vectors by guiding search methods. In addition, fault simulators are used for generating fault dictionaries for diagnosis and for computing aliases in signature analysis; in both cases all faults must be simulated for the entire test sequence. These two applications require a very fast fault simulator with a very efficient memory. Three simulation methods, concurrent fault simulation, parallel pattern single fault simulation and parallel fault simulation combined with single fault propagation are notable due to their efficiency, flexibility and /or versatility. One of the oldest methods for sequential circuit fault simulation is concurrent fault simulation. In this technique, a fault-free circuit and all the faulty circuits are simulated simultaneously. The biggest advantage of concurrent fault simulation lies in its flexibility and versatility. It can easily accommodate various delay models and functional modules. But it is quite slow and requires a lot of memory. Single fault propagation was originally developed for combinational circuits. In this technique, faults are simulated one at a time, under the application of a test pattern, and only the differences from the good circuit are simulated. This technique requires significantly less memory than concurrent fault simulation. This method was substantially improved later by simulating multiple patterns simultaneously and termed parallel pattern single fault simulation (PPSFP). Mojtahedi and Geisselhardt proposed a new fault simulator, COMBINED which combines the original single pattern single fault propagation method and the PPSFP technique [8]. In COMBINED, faults are initially simulated by applying one pattern at a time. After a certain number of faults are detected, any remaining faults are simulated using the PPSFP technique. This is an example of parallel fault simulation combined with single fault propagation [6]. III. PROOFS Cheng and Yu proposed a differential parallel fault simulator (DSIM) which is based on single fault propagation [9]. Like single fault propagation, DSIM simulates one fault at a time; but the difference is that DSIM simulates each fault, except the first based on the previous fault simulation result, while single fault propagation processes all faults based on the fault-free circuit simulation. The use of the previous fault simulation result enables DSIM to avoid restoring fault-free values before simulating each fault. Cheng et al. incorporated parallel fault simulation into DSIM. This new fault simulator, PROOFS simulates a packet of 32 faults in parallel [3]. The PROOFS fault simulation algorithm can be thought of as a hybrid of the concurrent, differential and parallel fault simulation algorithms. It retains the advantage of fault dropping that concurrent fault simulation allows, while exploiting the word level parallelism of the computer and retaining the low memory requirement of differential fault simulation. It uses a dynamic fault grouping strategy to fully utilize all the bit spaces


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AUBURN ELEC 7250 - SEQUENTIAL PARALLEL FAULT SIMULATOR

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