To Generate a Single Test Vector to detect all/most number of faults in a given setProblem StatementBackground workATPG / Vector Detection AlgorithmSnap Shot of the applicationSuggested ImprovementsResultsConclusionReferences4/28/054/28/05Raghuraman: ELEC7250Raghuraman: ELEC725011To Generate a Single Test Vector to detect To Generate a Single Test Vector to detect all/most number of faults in a given setall/most number of faults in a given setProject by: Arvind RaghuramanProject by: Arvind RaghuramanCourse ProjectCourse ProjectELEC 7250ELEC 72504/28/054/28/05Raghuraman: ELEC7250Raghuraman: ELEC725022Problem StatementProblem StatementThe Objective of the project is to determine a The Objective of the project is to determine a test vector that could detect all/most number of test vector that could detect all/most number of faults in a given set.faults in a given set.As a suggested improvement investigation was As a suggested improvement investigation was done on extending the algorithm developed for done on extending the algorithm developed for test set compaction.test set compaction.4/28/054/28/05Raghuraman: ELEC7250Raghuraman: ELEC725033Background work Background work Major Combinational ATPG Algorithms:Major Combinational ATPG Algorithms:•D-Algorithm (Roth) -- 1966 D-Algorithm (Roth) -- 1966 •PODEM (Goel) – 1981PODEM (Goel) – 1981Advanced ATPG Algorithms:Advanced ATPG Algorithms:•FAN – FAN – Multiple BacktraceMultiple Backtrace (1983) (1983)•TOPS – TOPS – DominatorsDominators (1987) (1987)•SOCRATES – SOCRATES – LearningLearning (1988) (1988)•Legal Assignments (1990)Legal Assignments (1990)•EST – EST – Search space learningSearch space learning (1991) (1991)•BDD Test generation (1991)BDD Test generation (1991)•Implication GraphsImplication Graphs and and Transitive ClosureTransitive Closure (1988 - 97) (1988 - 97)•Recursive LearningRecursive Learning (1995) (1995)4/28/054/28/05Raghuraman: ELEC7250Raghuraman: ELEC725044ATPG / Vector Detection AlgorithmATPG / Vector Detection AlgorithmCombinational circuit ATALANTA ATPGSET – Fn {TFn1, TFn2, ....TFnm}F1 - > (TFn1) = {TV1,TV4,TV6}F2 - > (TFn2) = {TV7, TV8,TV6,TV1}F3- > (TFn3) = {TV27, TV5,TV6,TV13}…….. TFnmOutput From ATALANTA ATPGEquivalence Collapsing and ATPGBench file for the given combinational circuitSET - TVFn = {TVFn1, TVFn2, ....TVFnm}TV1 - > (TVFn1) = {f1,f4,f6}TV2 - > (TVFn2) = {f7,f8,f6,f1}TV3- > (TVFn3) = {f27,f5,f6,f13}…….. TVFnmSet ManipulationR = MAXIMUM Set Size (SET - TVFnm) TVxTest Vector TVxDetects the most / All Faults in the givencombinational Circuit4/28/054/28/05Raghuraman: ELEC7250Raghuraman: ELEC725055Snap Shot of the applicationSnap Shot of the application4/28/054/28/05Raghuraman: ELEC7250Raghuraman: ELEC725066Suggested ImprovementsSuggested ImprovementsTest Compaction strategy:Test Compaction strategy:•The vector The vector TVx and the faults detected by the vector are dropped from the parent lists.•Now by rerunning the same algorithm we get another vector that detects the most number of faults.•Repeat step 1.•By repeating the process and by keeping track of the fault coverage after every iteration we can obtain a compact test set with required fault coverage.4/28/054/28/05Raghuraman: ELEC7250Raghuraman: ELEC725077ResultsResultsCircuit under Test : c17.bench combinational circuitCircuit under Test : c17.bench combinational circuit Number of test patterns : 54Number of test patterns : 54 Fault coverage : 100.000 %Fault coverage : 100.000 % Number of collapsed faults : 22Number of collapsed faults : 22Application outputApplication outputTest Vector " 000xx " detects 1 faultsTest Vector " 001xx " detects 1 faultsTest Vector " 00xxx " detects 2 faultsTest Vector " 010xx " detects 3 faultsTest Vector " 0110x " detects 5 faultsTest Vector " 0111x " detects 3 faultsTest Vector " 100xx " detects 4 faultsTest Vector " 10111 " detects 1 faultsTest Vector " 101x0 " detects 1 faultsTest Vector " 101xx " detects 2 faultsTest Vector " 110xx " detects 3 faultsTest Vector " 11100 " detects 2 faultsTest Vector " 11101 " detects 1 faultsTest Vector " 11110 " detects 1 faultsTest Vector " 11111 " detects 1 faultsTest Vector " 1111x " detects 2 faultsTest Vector " 1x1xx " detects 1 faultsTest Vector " x0011 " detects 1 faultsTest Vector " x00x0 " detects 1 faultsTest Vector " x00x1 " detects 3 faultsTest Vector " x0101 " detects 3 faultsTest Vector " x0111 " detects 2 faultsTest Vector " x0xx0 " detects 1 faultsTest Vector " x101x " detects 1 faultsTest Vector " x10x0 " detects 1 faultsTest Vector " x10xx " detects 2 faultsTest Vector " x1100 " detects 1 faultsTest Vector " x110x " detects 1 faultsTest Vector " x111x " detects 2 faultsTest Vector " xx111 " detects 1 faultsApplication Result Test Vector " 0110x " detects 5 faults4/28/054/28/05Raghuraman: ELEC7250Raghuraman: ELEC725088ConclusionConclusionThe Application developed correctly identifies The Application developed correctly identifies the test vector of interest.the test vector of interest.The proposed strategy for test compaction The proposed strategy for test compaction should be tested on other circuits and its should be tested on other circuits and its performance should be ascertained.performance should be ascertained.The Application can be used as a Generic Tool The Application can be used as a Generic Tool for any combinational circuits, it can directly for any combinational circuits, it can directly accept the output file from ATALANTA and accept the output file from ATALANTA and generate the test vector of interest.generate the test vector of interest.4/28/054/28/05Raghuraman: ELEC7250Raghuraman: ELEC725099ReferencesReferencesClass Lecture Notes ELEC 7250Class Lecture Notes ELEC 7250Essentials of Electronic Testing, Michael Essentials of Electronic Testing, Michael L.Bushnell, Vishwani D.AgarwalL.Bushnell, Vishwani
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