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AUBURN ELEC 7250 - lec1

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Lecture 1 IntroductionVLSI Realization ProcessDefinitionsVerification vs. TestProblems of Ideal TestsReal TestsTesting as Filter ProcessCosts of TestingDesign for Testability (DFT)Present and Future*Cost of Manufacturing Testing in 2000ADRoles of TestingA Modern VLSI Device System-on-a-chip (SOC)Course Outline Part I: IntroductionCourse Outline (Cont.) Part II: Test MethodsCourse Outline (Cont.) Part III: DFTCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 1 1Lecture 1IntroductionLecture 1IntroductionVLSI realization processVerification and testIdeal and real testsCosts of testingRoles of testingA modern VLSI device - system-on-a-chipCourse outline Part I: Introduction to testing Part II: Test methods Part III: Design for testabilityCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 1 2VLSI Realization ProcessVLSI Realization ProcessDetermine requirementsWrite specificationsDesign synthesis and VerificationFabricationManufacturing testChips to customerCustomer’s needTest developmentCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 1 3DefinitionsDefinitionsDesign synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes.Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function.Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1 4Verification vs. Test Verification vs. Test Verifies correctness of design.Performed by simulation, hardware emulation, or formal methods.Performed once prior to manufacturing.Responsible for quality of design.Verifies correctness of manufactured hardware.Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardwareTest application performed on every manufactured device.Responsible for quality of devices.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1 5Problems of Ideal TestsProblems of Ideal TestsIdeal tests detect all defects produced in the manufacturing process.Ideal tests pass all functionally good devices.Very large numbers and varieties of possible defects need to be tested.Difficult to generate tests for some real defects. Defect-oriented testing is an open problem.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1 6Real TestsReal TestsBased on analyzable fault models, which may not map on real defects.Incomplete coverage of modeled faults due to high complexity.Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss.Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1 7Testing as Filter ProcessTesting as Filter ProcessFabricatedchipsGood chipsDefective chipsProb(good) = yProb(bad) = 1- yProb(pass test) = highProb(fail test) = highProb(fail test) = lowProb(pass test) = lowMostlygoodchipsMostlybadchipsCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 1 8Costs of TestingCosts of TestingDesign for testability (DFT) Chip area overhead and yield reduction Performance overheadSoftware processes of test Test generation and fault simulation Test programming and debuggingManufacturing test Automatic test equipment (ATE) capital cost Test center operational costCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 1 9Design for Testability (DFT)Design for Testability (DFT)DFT refers to hardware design styles or addedhardware that reduces test generation complexity.Motivation: Test generation complexity increasesexponentially with the size of the circuit.Logicblock ALogicblock BPIPOTestinputTestoutputInt.busExample: Test hardware applies tests to blocks Aand B and to internal bus; avoids test generationfor combined A and B blocks.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1 10Present and Future*Present and Future* Transistors/sq. cm 4 - 10M 18 - 39M Pin count 100 - 900 160 - 1475Clock rate (MHz) 200 - 730 530 - 1100Power (Watts) 1.2 - 61 2 - 96 Feature size (micron) 0.25 - 0.15 0.13 - 0.101997 -2001 2003 - 2006* SIA Roadmap, IEEE Spectrum, July 1999Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1 11Cost of Manufacturing Testing in 2000ADCost of Manufacturing Testing in 2000AD0.5-1.0GHz, analog instruments,1,024 digital pins: ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272MRunning cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/yearTest cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/secondCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 1 12Roles of TestingRoles of TestingDetection: Determination whether or not the device under test (DUT) has some fault.Diagnosis: Identification of a specific fault that is present on DUT.Device characterization: Determination and correction of errors in design and/or test procedure.Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1 13A Modern VLSI DeviceSystem-on-a-chip (SOC)A Modern VLSI DeviceSystem-on-a-chip (SOC)DSPcoreRAMROMInter-facelogicMixed-signalCodecDataterminalTransmissionmediumFigure 18.5 (page 605)Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1 14Course OutlinePart I: IntroductionCourse OutlinePart I: IntroductionBasic concepts and definitions (Chapter 1)Test process and ATE (Chapter 2)Test economics and product quality (Chapter 3)Fault modeling (Chapter 4)Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1 15Course Outline (Cont.)Part II: Test MethodsCourse Outline (Cont.)Part II: Test MethodsLogic and fault simulation (Chapter 5)Testability measures (Chapter 6)Combinational circuit ATPG (Chapter 7)Sequential circuit ATPG (Chapter 8)Memory test (Chapter 9)Analog test (Chapters 10 and 11)Delay test and IDDQ test (Chapters 12 and 13)Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1 16Course Outline (Cont.)Part III: DFTCourse Outline (Cont.)Part III: DFTScan design (Chapter 14)BIST (Chapter 15)Boundary scan and analog test bus (Chapters 16 and


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