VLSI TESTINGTOPICSAppendix-AFinal Project Report VLSI TESTING KASI L.K. ANBUMONY TOPICS (1) LOGIC SIMULATOR (2) HIERARCHICAL TO FLATTEN NETLIST CONVERSION (3) SIMULATION TABLE GENERATION-A Robust Logic Simulator using Dynamic Levelization Algorithm- Section 1: Algorithm Implemented Step 1: Read the input and output net names in a dynamically growing array, netnameI and netnameO respectively Step 2: Assign values to the input name using another dynamically growing array, netvalueI and netvalueO respectively Step 3: Inputs are assigned on the rule of 2^N, where N: number of inputs in the circuit Step 4: Next netlists (or) statements in the Bench Circuit Description Language used in describing the logic are read one by one Step 5: Compare the input nets of the given gate with netnameI. If all the input nets of the given gate are found in the netnameI, then read out the netvalueI to solve the logic using “solve-user defined function” else goto Step 7 Step 6: The new output net of the gate evaluated in Step 5 is appended to the netnameI and its value to netvalueI Step 7: The netlist or statement which is not evaluated due to lack of data are then stored in another dynamically growing array-unfinish Step 8: Proceed executing next statements in circuit file, sequentially. Step 9: After every successful execution of given statement (or equivalently resolving the logic for that gate), the unfinished nets are visited once again due to the new condition of the circuit (netnameI & netvalueI) by calling the “redo- user defined function” (Dynamic Levelization) Step 10: By the time the program executes the last statement in the netlist all other logics in the circuit are resolved. Functions created in MATLAB and their purpose (i) logicsim: Main function which reads in the circuit file and simulates the circuit and stores the truth table of the given circuit in result.txt and CPU time in cputime.txt (ii) expand: If a given circuit description has hierarchy then this subroutine flattens the circuit and stores the netlist in Flat.txt (iii) solve: To resolve the logic of a given gate, given the gate name and gate nets. This function resolve gate with any number of inputs based on the associativity property. (iv) redo: Dynamic Levelization is implemented by means of feedback from the logicsim main function to redo function. Section 2: User Information Bench file should be in the format given in http://www.fm.vslib.cz/~kes/asic/iscas/*Type logicsim in MATLAB command window, will prompt for the filename *It then asks whether the file is in hierarchy (or) flatten format. -> Type 0 for hierarchical and 1 for Flatten. This helps in flattening the circuit if the circuit is in hierarchical format *Circuit need not be levelized because a kind of “Dynamic Levelization algorithm” has been implemented FlowchartStartRead the input andoutput netnamesnetnameI+netnameOAssign values to input netsnetvalueIInputs are assigned logical values(2^N)while! (EOF(*.bench))Input netsofgiven gate==netnameI?Gate evaluated and output netadded to netnameI and netvalueIStore the unfinished netsin an arrayrepeat until EOFAll Inputs havenetvalueIdefined?AND,OR,NAND,NOR-Any fanincontrol value?StopIs unfinishedempty?YesYes NoYesNoYesNoMethod 1Method 2Dynamic Levelization Section 3: Adder verification and diagnosis->Verification is produced in Appendix-A. Section 4: Diagnosis method Device after fabricated INPUTS OUTPUTSFault Dictionary Fault Test syndrome t1 t2 t3 t4No fault a0, b0, d0 a1 b1 c0 c1, d1, e1 e0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 a0 : Line a stuck- at-0 ti = 0, if Ti passes 1, if Ti fails Algorithm 1. Creation of fault dictionary for the specific circuit exhaustively for all stuck-at faults and bridge faults 2. Compare the good circuit and faulty circuit response to generate a signature for all test vectors listed in “fault dictionary” netname_good[] compare with netname_fault[] netvalue_good[] compare with netvalue_fault[] 3. Compare the signature with the signatures in the fault dictionary 4. Any match, then higher probability of fault existing of that type or other faults close to that nets 5. Update the fault list dictionary, if any new faults for the same signature found 6. Use minimum hamming distance to find a closer fault, if no signature match and verify those nets for possible faults Note: AUSIM and Atalanta can be used to generate Fault Dictionary for bridge faults and stuck-at faults respectively.Wrong net connection can be predicted using backtracing. Here from the output pin, a correct value is justified in backwards. The point where in the justification fails, all the gates and paths found from that point to output pin is reported (fault cone 1). Similar analysis is done on other test vectors wherein the combinational logic fails. Thus a a set of fault cones are formed and they can be intersected to find the gate or path which is occurring number of times. 0 1 0 0 1 01(0) Sample Outputs dict.txt max=3 # # # 0 0 0 0 a0 b0 d0 0 0 0 1 a1 # # 1 0 0 0 b1 # # 0 0 1 0 c0 # # 0 1 0 0 c1 d1 e1 1 0 1 0 e0 # # 0 1 0 1 #True circuit INPUT(1) INPUT(2) INPUT(3) OUTPUT(5) 4=AND(1,2) 5=OR(4,3) #faulty circuit INPUT(1) INPUT(2) INPUT(3) OUTPUT(5) 4=AND(1,2) 5=AND(4,3) Possible matching faults # means no fault 'e0' '#' '#' When response for the test vector set yields a signature status=[1 1 1 1]; Closely matched faults using minimum hamming ans ='c1' 'd1' 'e1' 'e0' '#' '#' Section 5: Examination of Performance (1) Plot CPU time vs. number of vectors for 4-bit adder circuit Method 1: If the netlist is levelized with n gates and an average fanin of each gate is k, then complexity is given by O(kn) Method 2: If one of the fanin’s of a logic gate is a control value (i.e.) for an AND gate it is 0, then we need not wait for other fanin’s for that gate to get stabilized. Saving by a factor of say “k1”. Other gates: OR,NOR,NAND. Complexity of Method 2 8765432187654321:)()()()()1()1()1()1(nnnnnnnnnNotenOnOknOknOkknOkknOkknOkknOnotbuffxnorxorornorandnand+++++++=+++++++= MATLAB Version: 7.0.4.365 (R14) Service Pack 2 Machine: Intel ® Celeron ™ CPU 1.19 GHz with 384 MB RAM(2) Plot CPU time vs. number of gates for ISCAS’85 circuits each simulated for 1000 random vectorsAppendix-A