Logic simulator and fault diagnosisMotivationsCompilerLogic SimulationLogic Simulation (Cont.)Slide 6Slide 7Some Comments on logic simulatorDiagnosis (Sensitized Path Segmentation + PO trace back)Slide 10Slide 11Logic simulator and fault diagnosisLogic simulator and fault diagnosisFan WangFan WangDept. of Electrical & Computer Engineering Dept. of Electrical & Computer Engineering Auburn UniversityAuburn UniversityELEC7250 Term Project Spring 06’ELEC7250 Term Project Spring 06’MotivationsMotivationsWrite a Write a compilercompiler for the hierarchical bench for the hierarchical bench format.format.Write a Write a logic simulatorlogic simulator for combinational for combinational circuitcircuitAttempt to Attempt to diagnosediagnose the design error the design errorCompiler Compiler For hierarchical bench For hierarchical bench format, the compiler can format, the compiler can flatten itflatten itCompiler can use Compiler can use flattened netlist to flattened netlist to generate the simulation generate the simulation table table For convenience, this For convenience, this part is implemented by part is implemented by Matlab.Matlab.Simulation table Example (generated by matlab)INPUT: 0INPUT: 1INPUT: 2OUTPUT: 15OUTPUT: 16Gatetype: XORGatename: XOR1Fanin_List: 2 1Fanout_List: FA_1_1/***************************/Gatetype: ANDGatename: AND1Fanin_List: 1 2Fanout_List: FA_1_2/***************************/Gatetype: ANDGatename: AND2Fanin_List: 0 FA_1_1Fanout_List: FA_1_3/***************************/Gatetype: XORGatename: XOR2Fanin_List: FA_1_1 0Fanout_List: 3/***************************/Logic SimulationLogic Simulation1.1.Read vector to the PIRead vector to the PI2.2.Initialize all the PO, Internal nodes as Initialize all the PO, Internal nodes as unknown states (-1).unknown states (-1).3.3.Propagate the value from PI to PO.Propagate the value from PI to PO. FFor each unknown internal node, search all file until it gets or each unknown internal node, search all file until it gets value. If all the PO get value, step 3 end.value. If all the PO get value, step 3 end.4.4.Repeat 1 to get the next vector.Repeat 1 to get the next vector.* Implemented by C program* Implemented by C programLogic Simulation (Cont.)Logic Simulation (Cont.)Some Comments on logic simulatorSome Comments on logic simulatorThe search based algorithm:The search based algorithm:1.1.Time complexity is O( ), N: the number of Time complexity is O( ), N: the number of gates. The worst case is, all gates are list in gates. The worst case is, all gates are list in reverse order. The time complexity is reverse order. The time complexity is The depth of circuit xThe depth of circuit x2. 2. The levelization of the circuit, the time The levelization of the circuit, the time complexity will the same as the logic simulation complexity will the same as the logic simulation based search based algorithmbased search based algorithmBetter algorithm can be used: link list based Better algorithm can be used: link list based algorithmalgorithm2N2NDiagnosis Diagnosis (Sensitized Path Segmentation + PO trace back)(Sensitized Path Segmentation + PO trace back)Check PO, see whether the PO get values as expectedCheck PO, see whether the PO get values as expectedIf error happens:If error happens: 1.1. trace back from the error PO to PI to check the paths trace back from the error PO to PI to check the paths (PATH 1). (PATH 1). 2.2. check which path is sensitized by the vector from PI to check which path is sensitized by the vector from PI to PO (PATH 2).PO (PATH 2).The error is on the path : PATH 1 PATH2The error is on the path : PATH 1 PATH2* Not for multiple fault diagnosis* Not for multiple fault diagnosis125893410Design error: OR --> AND !!(PI) 1 2 3 4(PI) 1 2 3 4 (PO Good Value) (PO Good Value) (PO Bad Value)(PO Bad Value)V1 0 0 0 1V1 0 0 0 1 0 0 00V2 0 0 1 1V2 0 0 1 1 0011V3 1 1 1 1V3 1 1 1 1 00 00V4 1 0 1 1V4 1 0 1 1 00 11p3p1* Based on 4 vectors: error is on p3 p2 p1 Sensitized path
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