Lecture 23 Design for Testability (DFT): Full-Scan (Lecture 19alt in the Alternative Sequence)DefinitionAd-Hoc DFT MethodsScan DesignScan Design RulesCorrecting a Rule ViolationScan Flip-Flop (SFF)Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)Adding Scan StructureComb. Test VectorsSlide 11Testing Scan RegisterMultiple Scan RegistersScan OverheadsHierarchical ScanOptimum Scan LayoutScan Area OverheadExample: Scan LayoutATPG Example: S5378Automated Scan DesignTiming and PowerSummaryCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt 1Lecture 23Design for Testability (DFT): Full-Scan(Lecture 19alt in the Alternative Sequence)Lecture 23Design for Testability (DFT): Full-Scan(Lecture 19alt in the Alternative Sequence)DefinitionAd-hoc methodsScan designDesign rulesScan registerScan flip-flopsScan test sequencesOverheadsScan design systemSummaryCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt 2DefinitionDefinitionDesign for testability (DFT) refers to those design techniques that make test generation and test application cost-effective.DFT methods for digital circuits:Ad-hoc methodsStructured methods:ScanPartial ScanBuilt-in self-test (BIST)Boundary scanDFT method for mixed-signal circuits:Analog test busCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt 3Ad-Hoc DFT MethodsAd-Hoc DFT MethodsGood design practices learnt through experience are used as guidelines:Avoid asynchronous (unclocked) feedback.Make flip-flops initializable.Avoid redundant gates. Avoid large fanin gates.Provide test control for difficult-to-control signals.Avoid gated clocks.Consider ATE requirements (tristates, etc.)Design reviews conducted by experts or design auditing tools.Disadvantages of ad-hoc DFT methods:Experts and tools not always available.Test generation is often manual with no guarantee of high fault coverage.Design iterations may be necessary.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt 4Scan DesignScan DesignCircuit is designed using pre-specified design rules.Test structure (hardware) is added to the verified design:Add a test control (TC) primary input.Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode.Make input/output of each scan shift register controllable/observable from PI/PO.Use combinational ATPG to obtain tests for all testable faults in the combinational logic.Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt 5Scan Design RulesScan Design RulesUse only clocked D-type of flip-flops for all state variables.At least one PI pin must be available for test; more pins, if available, can be used.All clocks must be controlled from PIs.Clocks must not feed data inputs of flip-flops.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt 6Correcting a Rule ViolationCorrecting a Rule ViolationAll clocks must be controlled from PIs.Comb.logicComb.logicD1D2CKQFFComb.logicD1D2CKQFFComb.logicCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt 7Scan Flip-Flop (SFF)Scan Flip-Flop (SFF)DTCSDCKQQMUXD flip-flopMaster latch Slave latchCKTCNormal mode, D selected Scan mode, SD selectedMaster openSlave openttLogicoverheadCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt 8Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)DSDMCKQQD flip-flopMaster latch Slave latchtSCKTCKSCKMCKTCKNormalmodeMCKTCKScanmodeLogicoverheadCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt 9Adding Scan StructureAdding Scan StructureSFFSFFSFFCombinationallogicPIPOSCANOUTSCANINTC or TCKNot shown: CK orMCK/SCK feed allSFFs.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt 10Comb. Test VectorsComb. Test Vectors I2 I1O1O2S2S1N2N1CombinationallogicPIPresentstatePONextstateSCANINTCSCANOUTCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt 11Comb. Test VectorsComb. Test Vectors I2 I1O1O2PIPOSCANINSCANOUT S1 S2 N1 N2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0TCDon’t careor randombitsSequence length = (ncomb + 1) nsff + ncomb clock periodsncomb = number of combinational vectorsnsff = number of scan flip-flopsCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt 12Testing Scan RegisterTesting Scan RegisterScan register must be tested prior to application of scan test sequences.A shift sequence 00110011 . . . of length nsff+4 in scan mode (TC=0) produces 00, 01, 11 and 10 transitions in all flip-flops and observes the result at SCANOUT output.Total scan test length: (ncomb + 2) nsff + ncomb + 4 clock periods.Example: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~ 106 clocks.Multiple scan registers reduce test length.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt 13Multiple Scan RegistersMultiple Scan RegistersScan flip-flops can be distributed among any number of shift registers, each having a separate scanin and scanout pin.Test sequence length is determined by the longest scan shift register.Just one test control (TC) pin is essential.SFFSFFSFFCombinationallogicPI/SCANINPO/SCANOUTMUXCKTCCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt 14Scan OverheadsScan OverheadsIO pins: One pin necessary.Area overhead:Gate overhead = [4 nsff/(ng+10nsff)] x 100%, where ng = comb. gates; nff = flip-flops; Example – ng = 100k gates, nsff = 2k flip-flops, overhead = 6.7%.More accurate estimate must consider scan wiring and layout area.Performance overhead:Multiplexer delay added in combinational path; approx. two gate-delays.Flip-flop output loading due to one additional fanout; approx. 5-6%.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt 15Hierarchical ScanHierarchical ScanScan flip-flops are chained within subnetworks before chaining subnetworks.Advantages:Automatic scan insertion in netlistCircuit hierarchy preserved – helps in debugging and design changesDisadvantage: Non-optimum chip layout.SFF1SFF2SFF3SFF4SFF3SFF1SFF2SFF4ScaninScanoutScaninScanoutHierarchical netlistFlat layoutCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt 16Optimum Scan LayoutOptimum Scan