CIRCULAR BUILT-IN SELF-TEST By Sudheer Vemula Electrical and Computer Engineering Dept. Auburn University (Class Project for VLSI Testing ELEC 7250)ABSTRACT: - A program to implement Circular BIST for any circuit described in Auburn Simulation Language (ASL) has been developed. Circular BIST has been implemented for the circuit S5378 and the fault simulation results have been analyzed. The code is written in ‘C’- Language and ASL tools have been used to convert the circuit net list from HITEC to ASL. Fault simulation is performed using Auburn University Simulator (AUSIM). INTRODUCTION:- The basic idea of BIST is to make the circuit test itself. The difficulty to test the VLSI chips has been increasing continuously. The number of I/O pins for most VLSI devices has increased by an order of magnitude where as the number of transistors has increased by four orders of magnitude. In-circuit testing of most circuits became infeasible because of the introduction of the surface mounted components, where the components are placed on both sides of the Printed Circuit Board (PCB). The cost of the test equipment is increasing as they are required to handle larger no. of I/O pins, higher operating frequencies, and are required to generate larger sets of test vectors. All the above mentioned difficulties can be minimized by the implementation of BIST in the circuits. In order to implement BIST we need to include extra circuitry. The extra circuitry consists of Test Pattern Generator (TPG), to generate the test patterns, the Output Response Analyzer (ORA), to compact the test results and the Test controller to control the test. BASIC BIST ARCHITECTURES:- Built-in Logic Block Observer (BILBO) was the first BIST approach that was proposed and was widely used. Its architecture is as shown in the fig.1. This BIST structure was implemented by converting the normal flip-flops in BILBO flip-flops. The BILBO structure is used both as a TPG and ORA. This can be operated in four modes of operation as given in table 1. Fig. 1 Built-in Logic Block ObserverB2 B1 Mode of Operation 0 0 Shift (scan) mode 0 1 MISR (BIST) mode1 0 Initialization Mode 1 1 System mode Table 1. Modes of operation of BILBO The application and operation of BILBO is shown in fig. 2. BILBO is a test-per-clock BIST architecture. Fig. 2 Simple BILBO application to a CUT This approach has been modified into a test per clock Circular BIST approach by connecting all the flip-flops in the form of a circular chain and operating the flip-flops in the BIST mode. And the basic flip-flop architecture has been slightly modified from the initial one. Three different circular BIST approaches have been proposed. They are Circular Self-Test path (CSTP), Simultaneous Self-Test (SST) and Circular BIST. (a) CSTP flip-flop and modes of operation B0 Xi Mode 0 Di System 1 Di ⊕ Qi-1 BIST Scan ModeB0 Xi Mode 0 0 0 Initialization0 1 Di System 1 0 Qi-1 Shift(Scan) (b) SST flip-flop and modes of operation(c) Circular BIST flip-flop and modes of operation Fig 3. Comparison of circular BIST flip-flops The basic idea of all these approaches is to partition the circuit into flip-flops and combinational logic and the flip-flops are augmented with additional logic to operate in BIST mode to test the circuit. The circular BIST approach forms a large Multiple Input Signature Register (MISR) structure connecting all the flip-flops in the circuit. The output of the MISR for the current cycle will be applied as the input for the next cycle. As we are using an MISR the output responses are also being compacted simultaneously. The circular feed back path is equivalent to a characteristic polynomial P(x) = xn + 1, where ‘n’ is the number of flip-flops. AREA OVERHEAD DUE TO FLIP-FLOPS:- The area over head for CSTP flip-flop is an ex-or gate and a multiplexer. It has an overhead of 7 gates, if we assume a 2-to-1 multiplexer is made up of 3 elementary logic gates and an ex-or with 4 gates. The main disadvantage is that it does no have scan mode. The area overhead for SST flip-flop is 9 gates and for Circular BIST flip-flop is 6 gates. The circular BIST approach has the lowest area overhead and it has 4 possible modes of operation including scan and initialization mode. MY WORK:- The Circular BIST approach has been used, for implementing the circular BIST for s5378, as it has the lowest area and highest flexibility (not required for this project). All the flip-flops, outputs and inputs of the circuit have been replaced by the circular BIST flip-flop shown in fig. 3c. . PROCEDURE TO IMPLEMENT CIRCULAR BIST:- 1) The file in ‘bench’ format has to be converted in to ASL file. This is done using the tools provide by Dr. Stroud, the command is ~strouce/bin/isc2asl name.bench, name.asl file is created. B1 B0 Xi Mode 0 0 0 Initialization 0 1 Di System 1 0 Qi-1 Shift(Scan) 1 1 Di ⊕ Qi-1BIST2) Circular BIST can be implemented by executing the provided program. This can be done using the commands cc name.c , An executable a.out is created, then the command a.out name.asl cbistname.asl (name.asl is the input ASL file and cbistname.asl is the output ASL file with the Circular BIST inserted). 3) After the Circular BIST has been implemented, fault coverage by implementing the Circular BIST has to be calculated. Fault coverage can be calculated by using fault simulation. Procedure to perform Fault Simulation using ASL:- a) The vector file (cbistname.vec) has to be created with the no. of inputs + 2. The two additional inputs are the control lines to control the operation of the circuit. The no. of vectors decide the no. of cycle for which the circuit has to be run in BIST mode. b) The control file (cbistname.cnt) has to be created. This file contains the commands to generate fault list and perform the logic and fault simulation. (Once the fault simulation has been done, we can find the fault profile). EFFICIENCY OR COVERAGE :- As the circuit is a sequential circuit, the test generation is difficult when compared to the combinational circuit. So, the vectors produced by HITEC do not give good enough fault coverage because of the difficulty in controlling the state of the flip flops. ADVANTAGES:- The testing is performed by the BIST circuitry at the system clock frequency; this helps in the detection of delay faults also. POSSIBLE IMPROVEMENTS:- Once full circular BIST has been implemented,