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AUBURN ELEC 7250 - Logic Simulator for Combinational Circuit

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Logic Simulator for Combinational CircuitProblem StatementLogic SimulatorSimulation TableAn Example of Simulation TableLogic PropagationAn Example of Logic PropagationResults for a 4-bit Ripple AdderResults for ISCAS’85 CircuitsFault DiagnosisConclusionSlide 1204/25/200604/25/2006ELEC 7250 Final Project: Jie QinELEC 7250 Final Project: Jie Qin11Logic Simulator for Logic Simulator for Combinational Combinational CircuitCircuitJie QinJie QinDept. of Electrical and Computer EngineeringDept. of Electrical and Computer EngineeringAuburn University, AL 36849, USAAuburn University, AL 36849, USA04/25/2006 ELEC 7250: Jie Qin 2Problem StatementProblem Statement►Develop a logic simulator with support Develop a logic simulator with support for the standard bench format and the for the standard bench format and the hierarchical bench format.hierarchical bench format.►When the output of the simulated When the output of the simulated circuit does not match the expected circuit does not match the expected response, try to diagnose the error in response, try to diagnose the error in the circuit using the logic simulator.the circuit using the logic simulator.04/25/2006 ELEC 7250: Jie Qin 3Logic SimulatorLogic Simulator►The implemented logic simulator The implemented logic simulator consists of a compiler and a simulator.consists of a compiler and a simulator. -- the compiler reads in a circuit description in -- the compiler reads in a circuit description in bench format and builds a bench format and builds a simulation tablesimulation table in in memory. memory. -- the simulator propagates the values provided -- the simulator propagates the values provided from outside at the PIs to the POs utilizing the from outside at the PIs to the POs utilizing the simulation table (simulation table (logic propagationlogic propagation). ).04/25/2006 ELEC 7250: Jie Qin 4Simulation TableSimulation Table►A simulation table is A simulation table is actually a list of gate actually a list of gate records. All the PIs, gates records. All the PIs, gates and POs in a circuit are and POs in a circuit are represented by the gate represented by the gate records in the implemented records in the implemented logic simulator. A gate logic simulator. A gate record includes the record includes the following information.following information.IDIDNameNameClassClassFanin list (FIL)Fanin list (FIL)Fanout list (FOL)Fanout list (FOL)Fanin’s value (FIFanin’s value (FIV)V)Gate’s value Gate’s value (GV)(GV)04/25/2006 ELEC 7250: Jie Qin 5An Example of Simulation TableAn Example of Simulation Tablegate “d” gate “e” PI “a” PO “f”gate “d” gate “e” PI “a” PO “f”ID: 4ID: 4Name: fName: fClass: POClass: POFIL: {e}FIL: {e}FOL: {f}FOL: {f}FIV: {-1}FIV: {-1}GV: {-1}GV: {-1}ID: 1ID: 1Name: dName: dClass: ANDClass: ANDFIL: {a, a}FIL: {a, a}FOL: {e}FOL: {e}FIV: {-1, FIV: {-1, -1}-1}GV: {-1}GV: {-1}a d e f ID: 3ID: 3Name: aName: aClass: PIClass: PIFIL: {a}FIL: {a}FOL: {d}FOL: {d}FIV: {-1}FIV: {-1}GV: {-1}GV: {-1}ID: 2ID: 2Name: eName: eClass: Class: NOTNOTFIL: {d}FIL: {d}FOL: {f}FOL: {f}FIV: {-1}FIV: {-1}GV: {-1}GV: {-1} before logic propagationbefore logic propagation04/25/2006 ELEC 7250: Jie Qin 6Logic PropagationLogic Propagation►To propagate the known value at the PITo propagate the known value at the PIs to the POs, two lists are maintained is to the POs, two lists are maintained in the memory.n the memory. -- -- passive listpassive list: it includes all the “gate records” w: it includes all the “gate records” whose outputs are in unknown states.hose outputs are in unknown states. -- -- active listactive list: once a gate has its output in known : once a gate has its output in known state, it will be append to this list. However, after alstate, it will be append to this list. However, after all the fanouts of this gate are determined as a known l the fanouts of this gate are determined as a known value, it will be removed from this list.value, it will be removed from this list.04/25/2006 ELEC 7250: Jie Qin 7An Example of Logic An Example of Logic PropagationPropagationa b g f hHalf-Adder c d e 0 1 0 1 0 1 1 active listactive listpassive listpassive listabhgedcf1 0 0 1 1 0 1 104/25/2006 ELEC 7250: Jie Qin 8Results for a 4-bit Ripple Results for a 4-bit Ripple AdderAdder04/25/2006 ELEC 7250: Jie Qin 9Results for ISCAS’85 Circuits Results for ISCAS’85 Circuits04/25/2006 ELEC 7250: Jie Qin 10Fault DiagnosisFault Diagnosis►Assumption #1: the internal state of the CUT cannot Assumption #1: the internal state of the CUT cannot observed from the outsideobserved from the outside►Assumption #2: the possibility of single fault is much Assumption #2: the possibility of single fault is much higher than multiple faultshigher than multiple faults►Approach: Approach: -- Step #1: for each faulty PO, obtain a reversed -- Step #1: for each faulty PO, obtain a reversed logic cone from PO;logic cone from PO; -- Step #2: intersect the logic cones obtained in -- Step #2: intersect the logic cones obtained in Step #1;Step #1; -- Step #3: try more test vectors to obtain a logic -- Step #3: try more test vectors to obtain a logic cone as small as possible.cone as small as possible.04/25/2006 ELEC 7250: Jie Qin 11ConclusionConclusion►The execution time increases with the The execution time increases with the number of gates and the number of number of gates and the number of test vectors.test vectors.►The fault diagnosis still needs to be The fault diagnosis still needs to be improved because the assumption improved because the assumption does not match the real situation very does not match the real situation very well.well.04/25/2006 ELEC 7250: Jie Qin 12ThankThank


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AUBURN ELEC 7250 - Logic Simulator for Combinational Circuit

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