Lecture 7 Fault SimulationProblem and MotivationFault simulator in a VLSI Design ProcessFault Simulation ScenarioFault Simulation Scenario (Continued)Fault Simulation AlgorithmsSerial AlgorithmSerial Algorithm (Cont.)Parallel Fault SimulationParallel Fault Sim. ExampleDeductive Fault SimulationDeductive Fault Sim. ExampleConcurrent Fault SimulationConc. Fault Sim. ExampleFault SamplingMotivation for SamplingRandom Sampling ModelProbability Density of Sample Coverage, cSampling Error BoundsSummaryCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 7 1Lecture 7Fault SimulationLecture 7Fault SimulationProblem and motivationFault simulation algorithmsSerialParallelDeductiveConcurrentRandom Fault SamplingSummaryCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 7 2Problem and MotivationProblem and MotivationFault simulation Problem:GivenA circuitA sequence of test vectorsA fault modelDetermineFault coverage - fraction (or percentage) of modeled faults detected by test vectorsSet of undetected faultsMotivationDetermine test quality and in turn product qualityFind undetected fault targets to improve testsCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 7 3Fault simulator in a VLSI Design ProcessFault simulator in a VLSI Design ProcessVerified designnetlistVerificationinput stimuliFault simulator Test vectorsModeledfault listTestgeneratorTestcompactorFaultcoverage?Remove tested faultsDeletevectorsAdd vectorsLowAdequateStopCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 7 4Fault Simulation ScenarioFault Simulation ScenarioCircuit model: mixed-levelMostly logic with some switch-level for high-impedance (Z) and bidirectional signalsHigh-level models (memory, etc.) with pin faultsSignal states: logicTwo (0, 1) or three (0, 1, X) states for purely Boolean logic circuitsFour states (0, 1, X, Z) for sequential MOS circuitsTiming:Zero-delay for combinational and synchronous circuitsMostly unit-delay for circuits with feedbackCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 7 5Fault Simulation Scenario (Continued)Fault Simulation Scenario (Continued)Faults:Mostly single stuck-at faultsSometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common useEquivalence fault collapsing of single stuck-at faultsFault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosisFault sampling -- a random sample of faults is simulated when the circuit is largeCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 7 6Fault Simulation AlgorithmsFault Simulation AlgorithmsSerialParallelDeductiveConcurrentDifferential** Not discussed; see M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000, Chapter 5.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 7 7Serial AlgorithmSerial AlgorithmAlgorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list:Modify netlist by injecting one faultSimulate modified netlist, vector by vector, comparing responses with saved responsesIf response differs, report fault detection and suspend simulation of remaining vectorsAdvantages:Easy to implement; needs only a true-value simulator, less memoryMost faults, including analog faults, can be simulatedCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 7 8Serial Algorithm (Cont.)Serial Algorithm (Cont.)Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuitsAlternative: Simulate many faults togetherTest vectors Fault-free circuit Circuit with fault f1Circuit with fault f2Circuit with fault fnComparatorf1 detected?Comparatorf2 detected?Comparatorfn detected?Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 7 9Parallel Fault SimulationParallel Fault SimulationCompiled-code method; best with two-states (0,1)Exploits inherent bit-parallelism of logic operations on computer wordsStorage: one word per line for two-state simulationMulti-pass simulation: Each pass simulates w-1 new faults, where w is the machine word lengthSpeed up over serial method ~ w-1Not suitable for circuits with timing-critical and non-Boolean logicCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 7 10Parallel Fault Sim. ExampleParallel Fault Sim. Examplea b c d e f g 1 1 11 1 11 0 11 0 10 0 01 0 1s-a-1s-a-00 0 1c s-a-0 detectedBit 0: fault-free circuitBit 1: circuit with c s-a-0Bit 2: circuit with f s-a-1Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 7 11Deductive Fault SimulationDeductive Fault SimulationOne-pass simulationEach line k contains a list Lk of faults detectable on it Following true-value simulation of each vector, fault lists of all gate output lines are updated using set-theoretic rules, signal values, and gate input fault listsPO fault lists provide detection dataLimitations:Set-theoretic rules difficult to derive for non-Boolean gatesGate delays are difficult to useCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 7 12Deductive Fault Sim.ExampleDeductive Fault Sim.Examplea b c d e f g 11101{a0}{b0 , c0}{b0}{b0 , d0}Le = La U Lc U {e0} = {a0 , b0 , c0 , e0}Lg = (Le Lf ) U {g0} = {a0 , c0 , e0 , g0}U{b0 , d0 , f1}Notation: Lk is fault list for line k kn is s-a-n fault on line k Faults detected bythe input vectorCopyright 2001, Agrawal & BushnellVLSI Test: Lecture 7 13Concurrent Fault SimulationConcurrent Fault SimulationEvent-driven simulation of fault-free circuit and only those parts of the faulty circuit that differ in signal states from the fault-free circuit.A list per gate containing copies of the gate from all faulty circuits in which this gate differs. List element contains fault ID, gate input and output values and internal states, if any.All events of fault-free and all faulty circuits are implicitly simulated.Faults can be simulated in any modeling style or detail supported in true-value simulation (offers most flexibility.)Faster than other methods, but uses most memory.Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 7 14Conc. Fault Sim. ExampleConc. Fault Sim. Examplea b c d e f g 1110111110110010100100110100111111000011000000010111a0b0c0e0a0b0b0c0e0d0d0g0f1f1Copyright 2001, Agrawal & BushnellVLSI