15 213 The course that gives CMU its Zip Caches October 12 2000 Topics Memory Hierarchy Locality of Reference SRAM Caches Direct Mapped Associative class14 ppt Computer System Processor Processor interrupt Cache Cache Memory I O Memory I Obus bus Memory Memory I O I O controller controller disk Disk class14 ppt disk Disk 2 I O I O controller controller I O I O controller controller Display Display Network Network CS 213 F 00 Levels in Memory Hierarchy cache CPU CPU regs regs Register size speed Mbyte line size 200 B 3 ns 8B 8B C a c h e 32 B virtual memory Memory Memory Cache 32 KB 4MB 4 ns 100 MB 32 B Memory 128 MB 60 ns 1 50 MB 8 KB 8 KB disk disk Disk Memory 30 GB 8 ms 0 05 MB larger slower cheaper class14 ppt 3 CS 213 F 00 Alpha 21164 Chip Caches L3 Control Right Half L2 Caches L1 data L1 instruction L2 unified TLB Branch history L1 Data L1 I n s t r Right Half L2 class14 ppt 4 L2 Tags CS 213 F 00 Locality of Reference Principle of Locality Programs tend to reuse data and instructions near those they have used recently Temporal locality recently referenced items are likely to be referenced in the near future Spatial locality items with nearby addresses tend to be referenced close together in time Locality in Example sum 0 for i 0 i n i sum a i v sum Data Reference array elements in succession spatial Instructions Reference instructions in sequence spatial Cycle through loop repeatedly temporal class14 ppt 5 CS 213 F 00 Caching The Basic Idea Main Memory Stores words A Z in example Cache Small Fast Cache Processor Stores subset of the words 4 in example Organized in lines Multiple words To exploit spatial locality A B G H Big Slow Memory A B C Y Z Access Word must be in cache for processor to access class14 ppt 6 CS 213 F 00 Basic Idea Cont Initial Read C Read D Read Z A B A B A B Y Z G H C D C D C D Cache holds 2 lines Each with 2 words Load line C D into cache Cache miss Word already in cache Cache hit Load line Y Z into cache Evict oldest entry Maintaining Cache Each time the processor performs a load or store bring line containing the word into the cache May need to evict existing line Subsequent loads or stores to any word in line performed within cache class14 ppt 7 CS 213 F 00 Accessing Data in Memory Hierarchy Between any two levels memory is divided into lines aka blocks Data moves between levels on demand in line sized chunks Invisible to application programmer Hardware responsible for cache operation Upper level lines a subset of lower level lines Access word w in line a hit Access word v in line b miss w High Level v a a a b b Low Level b b a class14 ppt a 8 b a CS 213 F 00 Design Issues for Caches Key Questions Where should a line be placed in the cache line placement How is a line found in the cache line identification Which line should be replaced on a miss line replacement What happens on a write write strategy Constraints Design must be very simple Hardware realization All decision making within nanosecond time scale Want to optimize performance for typical programs Do extensive benchmarking and simulations Many subtle engineering tradeoffs class14 ppt 9 CS 213 F 00 Direct Mapped Caches Simplest Design Each memory line has a unique cache location Parameters Line or block size B 2b Number of bytes in each line Typically 2X 8X word size Number of Sets S 2s Number of lines cache can hold Total Cache Size B S 2b s m bit Physical Address t s Physical Address set index Address used to reference main memory tag m bits to reference M 2m total bytes Partition into fields Offset Lower b bits indicate which byte within line Set Next s bits indicate how to locate line within cache Tag Identifies this line when in cache class14 ppt 10 CS 213 F 00 b offset Indexing into Direct Mapped Cache Use set index bits to select cache set Set 0 Tag Valid 0 1 B 1 Set 1 Tag Valid 0 1 B 1 0 1 B 1 Set S 1 t s b tag set index offset Tag Valid Physical Address class14 ppt 11 CS 213 F 00 Direct Mapped Cache Tag Matching Identifying Line Must have tag match high order bits of address Must have Valid 1 Selected Set 1 Tag t s b tag set index offset Valid 0 1 Lower bits of address select byte or word within cache line Physical Address class14 ppt 12 B 1 CS 213 F 00 Direct Mapped Cache Simulation t 1 s 2 x xx b 1 x M 16 byte addresses B 2 bytes line S 4 sets E 1 entry set Address trace reads 0 0000 1 0001 13 1101 8 1000 0 0000 v 1 0 0000 miss tag data 0 m 1 m 0 1 2 v 1 8 1000 miss tag data 1 4 13 1 0 m 1 m 0 1 1 m 13 m 12 v m 9 m 8 3 class14 ppt 13 1101 miss v tag data 0 0000 miss tag data 1 0 m 1 m 0 1 1 m 13 m 12 CS 213 F 00 Why Use Middle Bits as Index High Order Bit Indexing 4 line Cache 00 01 10 11 High Order Bit Indexing Adjacent memory lines would map to same cache entry Poor use of spatial locality Middle Order Bit Indexing Consecutive memory lines map to different cache lines Can hold C byte region of address space in cache at one time class14 ppt 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 14 Middle Order Bit Indexing 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CS 213 F 00 Direct Mapped Cache Implementation DECStation 3100 31 30 29 19 18 17 16 15 14 13 5 4 3 2 1 0 byte tag set offset valid tag 16 bits data 32 bits 16 384 sets data hit class14 ppt 15 CS 213 F 00 Properties of Direct Mapped Caches Strength Minimal control hardware overhead Simple design Relatively easy to make fast Weakness Vulnerable to thrashing Two heavily used lines have same cache index Repeatedly evict one to make room for other Cache Line class14 ppt 16 CS 213 F 00 Vector Product Example float dot prod float x 1024 y 1024 float sum 0 0 int i for i 0 i 1024 i sum x i y i return sum Machine DECStation 5000 MIPS Processor with 64KB direct mapped cache 16 B line size Performance Good case 24 cycles element Bad case 66 cycles element class14 ppt 17 CS 213 F 00 Thrashing Example x 0 …
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