P6/Linux Memory System November 1, 2001Intel P6P6 memory systemReview of abbreviationsOverview of P6 address translationP6 2-level page table structureP6 page directory entry (PDE)P6 page table entry (PTE)How P6 page tables map virtual addresses to physical onesRepresentation of Virtual Address SpaceP6 TLB translationP6 TLBTranslating with the P6 TLBP6 page table translationTranslating with the P6 page tables (case 1/1)Translating with the P6 page tables (case 1/0)Translating with the P6 page tables (case 1/0, cont)Translating with the P6 page tables (case 0/1)Translating with the P6 page tables (case 0/0)Translating with the P6 page tables (case 0/0, cont)P6 L1 cache accessL1 cache accessSpeeding Up L1 AccessLinux organizes VM as a collection of “areas”Linux page fault handlingMemory mappingUser-level memory mappingmmap() example: fast file copyExec() revisitedFork() revistedMemory System SummaryP6/Linux Memory SystemNovember 1, 2001Topics•P6 address translation•Linux memory management•Linux page fault handling•memory mappingclass20.ppt15-213“The course that gives CMU its Zip!”CS 213 F’01– 2 –class20.pptIntel P6Internal Designation for Successor to Pentium•Which had internal designation P5Fundamentally Different from Pentium•Out-of-order, superscalar operation•Designed to handle server applications–Requires high performance memory systemResulting Processors•PentiumPro (1996)•Pentium II (1997)–Incorporated MMX instructions»special instructions for parallel processing–L2 cache on same chip•Pentium III (1999)–Incorporated Streaming SIMD Extensions»More instructions for parallel processingCS 213 F’01– 3 –class20.pptP6 memory systembus interface unitDRAMexternal system bus (e.g. PCI)instruction fetch unitL1i-cacheL2cachecache busL1d-cacheinstTLBdataTLBprocessor package• 32 bit address space• 4 KB page size• L1, L2, and TLBs• 4-way set associative• inst TLB• 32 entries• 8 sets• data TLB• 64 entries• 16 sets• L1 i-cache and d-cache• 16 KB• 32 B line size• 128 sets• L2 cache• unified• 128 KB -- 2 MBCS 213 F’01– 4 –class20.pptReview of abbreviationsSymbols:•Components of the virtual address (VA)–TLBI: TLB index–TLBT: TLB tag–VPO: virtual page offset –VPN: virtual page number •Components of the physical address (PA)–PPO: physical page offset (same as VPO)–PPN: physical page number–CO: byte offset within cache line–CI: cache index–CT: cache tagCS 213 F’01– 5 –class20.pptOverview of P6 address translationCPUVPN VPO20 12TLBT TLBI416virtual address (VA)...TLB (16 sets, 4 entries/set)VPN1 VPN21010PDE PTEPDBRPPN PPO20 12Page tablesTLBmissTLBhitphysicaladdress (PA)result32...CT CO20 5CI7L2 and DRAML1 (128 sets, 4 lines/set)L1hitL1missCS 213 F’01– 6 –class20.pptP6 2-level page table structurePage directory •1024 4-byte page directory entries (PDEs) that point to page tables•one page directory per process.•page directory must be in memory when its process is running•always pointed to by PDBRPage tables:•1024 4-byte page table entries (PTEs) that point to pages.•page tables can be paged in and out.page directory...Up to 1024 page tables1024PTEs1024PTEs1024PTEs...1024PDEsCS 213 F’01– 7 –class20.pptP6 page directory entry (PDE)Page table physical base addr Avail G PS A CD WT U/S R/W P=1Page table physical base address: 20 most significant bits of physical page table address (forces page tables to be 4KB aligned)Avail: available for system programmersG: global page (don’t evict from TLB on task switch)PS: page size 4K (0) or 4M (1)A: accessed (set by MMU on reads and writes, cleared by software) CD: cache disabled (1) or enabled (0)WT: write-through or write-back cache policy for this page tableU/S: user or supervisor mode accessR/W: read-only or read-write accessP: page table is present in memory (1) or not (0)31 12 11 9 8 7 6 5 4 3 2 1 0Available for OS (page table location in secondary storage) P=031 01CS 213 F’01– 8 –class20.pptP6 page table entry (PTE)Page physical base address Avail G 0 D A CD WT U/S R/W P=1Page base address: 20 most significant bits of physical page address (forces pages to be 4 KB aligned)Avail: available for system programmersG: global page (don’t evict from TLB on task switch)D: dirty (set by MMU on writes)A: accessed (set by MMU on reads and writes) CD: cache disabled or enabledWT: write-through or write-back cache policy for this pageU/S: user/supervisorR/W: read/writeP: page is present in physical memory (1) or not (0)31 12 11 9 8 7 6 5 4 3 2 1 0Available for OS (page location in secondary storage) P=031 01CS 213 F’01– 9 –class20.pptHow P6 page tables map virtualaddresses to physical onesPDEPDBRphysical addressof page table base(if P=1)physical addressof page base(if P=1)physical addressof page directoryword offset into page directoryword offset into page tablepage directory page tableVPN110VPO10 12VPN2Virtual addressPTEPPN PPO2012Physical addressword offset into physical and virtualpageCS 213 F’01– 10 –class20.pptRepresentation of Virtual Address SpaceSimplified Example•16 page virtual address spaceFlags•P: Is entry in physical memory?•M: Has this part of VA space been mapped?Page DirectoryPT 3P=1, M=1P=1, M=1P=0, M=0P=0, M=1••••P=1, M=1P=0, M=0P=1, M=1P=0, M=1••••P=1, M=1P=0, M=0P=1, M=1P=0, M=1••••P=0, M=1P=0, M=1P=0, M=0P=0, M=0••••PT 2PT 0Page 0Page 1Page 2Page 3Page 4Page 5Page 6Page 7Page 8Page 9Page 10Page 11Page 12Page 13Page 14Page 15Mem AddrDisk AddrIn MemOn DiskUnmappedCS 213 F’01– 11 –class20.pptP6 TLB translationCPUVPN VPO20 12TLBT TLBI416virtual address (VA)...TLB (16 sets, 4 entries/set)VPN1 VPN21010PDE PTEPDBRPPN PPO20 12Page tablesTLBmissTLBhitphysicaladdress (PA)result32...CT CO20 5CI7L2 andDRAML1 (128 sets, 4 lines/set)L1hitL1missCS 213 F’01– 12 –class20.pptP6 TLBTLB entry (not all documented, so this is speculative):•V: indicates a valid (1) or invalid (0) TLB entry•PD: is this entry a PDE (1) or a PTE (0)?•tag: disambiguates entries cached in the same set•PDE/PTE: page directory or page table entry•Structure of the data TLB:•16 sets, 4 entries/setPDE/PTE Tag PD V1 11632entry entry entry entryentry entry entry entryentry entry entry entryentry entry entry entry...set 0set 1set 2set 15CS 213 F’01– 13 –class20.pptTranslating with the P6 TLB1. Partition VPN into TLBT and TLBI.2. Is the PTE for VPN cached in set
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