Slide 1TodayReview of SymbolsSimple Memory System ExampleSimple Memory System Page TableSimple Memory System TLBSimple Memory System CacheAddress Translation Example #1Address Translation Example #2Address Translation Example #3TodayIntel Core i7 Memory SystemReview of SymbolsEnd-to-end Core i7 Address TranslationCore i7 Level 1-3 Page Table EntriesCore i7 Level 4 Page Table EntriesCore i7 Page Table TranslationCute Trick for Speeding Up L1 AccessVirtual Memory of a Linux ProcessLinux Organizes VM as Collection of “Areas”Linux Page Fault HandlingTodayMemory MappingDemand pagingSharing Revisited: Shared ObjectsSharing Revisited: Shared ObjectsSharing Revisited: Private Copy-on-write (COW) ObjectsSharing Revisited: Private Copy-on-write (COW) ObjectsThe fork Function RevisitedThe execve Function RevisitedUser-Level Memory MappingUser-Level Memory MappingUsing mmap to Copy FilesCarnegie Mellon1Virtual Memory: Systems15-213: Introduction to Computer Systems16th Lecture, Oct. 19, 2010Instructors: Randy Bryant and Dave O’HallaronCarnegie Mellon2TodaySimple memory system exampleCase study: Core i7/Linux memory systemMemory mappingCarnegie Mellon3Review of SymbolsBasic ParametersN = 2n : Number of addresses in virtual address spaceM = 2m : Number of addresses in physical address spaceP = 2p : Page size (bytes)Components of the virtual address (VA)TLBI: TLB indexTLBT: TLB tagVPO: Virtual page offset VPN: Virtual page number Components of the physical address (PA)PPO: Physical page offset (same as VPO)PPN: Physical page numberCO: Byte offset within cache lineCI: Cache indexCT: Cache tagCarnegie Mellon4Simple Memory System ExampleAddressing14-bit virtual addresses12-bit physical addressPage size = 64 bytes13 12 11 10 9 8 7 6 5 4 3 2 1 011 10 9 8 7 6 5 4 3 2 1 0VPOPPOPPNVPNVirtual Page NumberVirtual Page OffsetPhysical Page NumberPhysical Page OffsetCarnegie Mellon5Simple Memory System Page TableOnly show first 16 entries (out of 256)10D0F1110E12D0D0–0C0–0B1090A1170911308ValidPPNVPN0–070–06116050–0410203133020–0112800ValidPPNVPNCarnegie Mellon6Simple Memory System TLB16 entries4-way associative13 12 11 10 9 8 7 6 5 4 3 2 1 0VPOVPNTLBITLBT0–021340A10D030–0730–030–060–080–0220–0A0–040–0212D031102070–0010D090–030ValidPPNTagValidPPNTagValidPPNTagValidPPNTagSetCarnegie Mellon7Simple Memory System Cache16 lines, 4-byte block sizePhysically addressedDirect mapped11 10 9 8 7 6 5 4 3 2 1 0PPOPPNCOCICT03DFC2111167––––03161DF0723610D5098F6D431324––––03630804020011B2––––0151112311991190B3B2B1B0ValidTagIdx––––014FD31B7783113E15349604116D––––012C––––00BB3BDA159312DA––––02D98951003A1248B3B2B1B0ValidTagIdxCarnegie Mellon8Address Translation Example #1Virtual Address: 0x03D4VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____Physical AddressCO ___ CI___ CT ____ Hit? __ Byte: ____13 12 11 10 9 8 7 6 5 4 3 2 1 0VPOVPNTLBITLBT11 10 9 8 7 6 5 4 3 2 1 0PPOPPNCOCICT001010111100000x0F 0x3 0x03 Y N 0x0D0001010 110100 0x5 0x0D Y 0x36Carnegie Mellon9Address Translation Example #2Virtual Address: 0x0B8FVPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____Physical AddressCO ___ CI___ CT ____ Hit? __ Byte: ____13 12 11 10 9 8 7 6 5 4 3 2 1 0VPOVPNTLBITLBT11 10 9 8 7 6 5 4 3 2 1 0PPOPPNCOCICT111100011101000x2E 2 0x0B N Y TBDCarnegie Mellon10Address Translation Example #3Virtual Address: 0x0020VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____Physical AddressCO___ CI___ CT ____ Hit? __ Byte: ____13 12 11 10 9 8 7 6 5 4 3 2 1 0VPOVPNTLBITLBT11 10 9 8 7 6 5 4 3 2 1 0PPOPPNCOCICT000001000000000x00 0 0x00 N N 0x280000000 001110 0x8 0x28 N MemCarnegie Mellon11TodaySimple memory system exampleCase study: Core i7/Linux memory systemMemory mappingCarnegie Mellon12Intel Core i7 Memory SystemL1 d-cache32 KB, 8-wayL1 d-cache32 KB, 8-wayL2 unified cache256 KB, 8-wayL2 unified cache256 KB, 8-wayL3 unified cache8 MB, 16-way (shared by all cores)L3 unified cache8 MB, 16-way (shared by all cores)Main memoryMain memoryRegistersRegistersL1 d-TLB64 entries, 4-wayL1 d-TLB64 entries, 4-wayL1 i-TLB128 entries, 4-wayL1 i-TLB128 entries, 4-wayL2 unified TLB512 entries, 4-wayL2 unified TLB512 entries, 4-wayL1 i-cache32 KB, 8-wayL1 i-cache32 KB, 8-wayMMU (addr translation)MMU (addr translation)InstructionfetchInstructionfetchCore x4DDR3 Memory controller3 x 64 bit @ 10.66 GB/s32 GB/s total (shared by all cores)DDR3 Memory controller3 x 64 bit @ 10.66 GB/s32 GB/s total (shared by all cores)Processor packageQuickPath interconnect4 links @ 25.6 GB/s eachQuickPath interconnect4 links @ 25.6 GB/s eachTo other coresTo I/ObridgeCarnegie Mellon13Review of SymbolsBasic ParametersN = 2n : Number of addresses in virtual address spaceM = 2m : Number of addresses in physical address spaceP = 2p : Page size (bytes)Components of the virtual address (VA)TLBI: TLB indexTLBT: TLB tagVPO: Virtual page offset VPN: Virtual page number Components of the physical address (PA)PPO: Physical page offset (same as VPO)PPN: Physical page numberCO: Byte offset within cache lineCI: Cache indexCT: Cache tagCarnegie Mellon14End-to-end Core i7 Address TranslationCPUVPN VPO36 12TLBT TLBI432...L1 TLB (16 sets, 4 entries/set)VPN1 VPN299PTECR3PPN PPO40 12Page tablesTLBmissTLBhitPhysicaladdress (PA)Result32/64...CT CO40 6CI6L2, L3, and main memoryL1 d-cache (64 sets, 8 lines/set)L1hitL1missVirtual address (VA)VPN3 VPN499PTE PTEPTECarnegie Mellon15Core i7 Level 1-3 Page Table EntriesPage table physical base address Unused G PS A CD WT U/S R/W P=1Each entry references a 4K child page tableP: Child page table present in physical memory (1) or not (0).R/W: Read-only or read-write access access permission for all reachable pages.U/S: user or supervisor (kernel) mode access permission for all reachable pages.WT: Write-through or write-back cache policy for the child page table. CD: Caching disabled or enabled for the child page table. A: Reference bit (set by MMU on reads and writes, cleared by software).PS: Page size either 4 KB or 4 MB (defined for Level 1 PTEs only).G: Global page (don’t evict from TLB on task switch)Page table physical base address: 40 most significant bits of physical page table address (forces
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