The Memory Hierarchy Feb. 20, 2003Random-Access Memory (RAM)SRAM vs DRAM SummaryConventional DRAM OrganizationReading DRAM Supercell (2,1)Slide 6Memory ModulesEnhanced DRAMsNonvolatile MemoriesTypical Bus Structure Connecting CPU and MemoryMemory Read Transaction (1)Memory Read Transaction (2)Memory Read Transaction (3)Memory Write Transaction (1)Memory Write Transaction (2)Memory Write Transaction (3)Disk GeometryDisk Geometry (Muliple-Platter View)Disk CapacityComputing Disk CapacityDisk Operation (Single-Platter View)Disk Operation (Multi-Platter View)Disk Access TimeDisk Access Time ExampleLogical Disk BlocksI/O BusReading a Disk Sector (1)Reading a Disk Sector (2)Reading a Disk Sector (3)Storage TrendsCPU Clock RatesThe CPU-Memory GapLocalityLocality ExampleSlide 35Slide 36Memory HierarchiesAn Example Memory HierarchyCachesCaching in a Memory HierarchyGeneral Caching ConceptsGeneral Caching ConceptsExamples of Caching in the HierarchyThe Memory HierarchyFeb. 20, 2003The Memory HierarchyFeb. 20, 2003TopicsTopicsStorage technologies and trendsLocality of referenceCaching in the memory hierarchyclass12.ppt15-213“The course that gives CMU its Zip!”– 2 –15-213, S’03Random-Access Memory (RAM)Random-Access Memory (RAM)Key featuresKey featuresRAM is packaged as a chip.Basic storage unit is a cell (one bit per cell).Multiple RAM chips form a memory.Static RAM (Static RAM (SRAMSRAM))Each cell stores bit with a six-transistor circuit.Retains value indefinitely, as long as it is kept powered.Relatively insensitive to disturbances such as electrical noise.Faster and more expensive than DRAM.Dynamic RAM (Dynamic RAM (DRAMDRAM))Each cell stores bit with a capacitor and transistor.Value must be refreshed every 10-100 ms.Sensitive to disturbances.Slower and cheaper than SRAM.– 3 –15-213, S’03SRAM vs DRAM SummarySRAM vs DRAM SummaryTran. Accessper bit time Persist? Sensitive? Cost ApplicationsSRAM 6 1X Yes No 100x cache memoriesDRAM 1 10X No Yes 1X Main memories,frame buffers– 4 –15-213, S’03Conventional DRAM OrganizationConventional DRAM Organizationd x w DRAM:d x w DRAM:dw total bits organized as d supercells of size w bitscolsrows01 2 30123internal row buffer16 x 8 DRAM chipaddrdatasupercell(2,1)2 bits/8 bits/memorycontroller(to CPU)– 5 –15-213, S’03Reading DRAM Supercell (2,1)Reading DRAM Supercell (2,1)Step 1(a): Row access strobe (Step 1(a): Row access strobe (RASRAS) selects row 2.) selects row 2.colsrowsRAS = 201 2 3012internal row buffer16 x 8 DRAM chip3addrdata2/8/memorycontrollerStep 1(b): Row 2 copied from DRAM array to row buffer.Step 1(b): Row 2 copied from DRAM array to row buffer.– 6 –15-213, S’03Reading DRAM Supercell (2,1)Reading DRAM Supercell (2,1)Step 2(a): Column access strobe (Step 2(a): Column access strobe (CASCAS) selects column 1.) selects column 1.colsrows01 2 30123internal row buffer16 x 8 DRAM chipCAS = 1addrdata2/8/memorycontrollerStep 2(b): Supercell (2,1) copied from buffer to data lines, Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU.and eventually back to the CPU.supercell (2,1)supercell (2,1)To CPU– 7 –15-213, S’03Memory ModulesMemory Modules: supercell (i,j)64 MB memory moduleconsisting ofeight 8Mx8 DRAMsaddr (row = i, col = j)MemorycontrollerDRAM 7DRAM 0031 78151623243263 39404748555664-bit doubleword at main memory address Abits0-7bits8-15bits16-23bits24-31bits32-39bits40-47bits48-55bits56-6364-bit doubleword031 78151623243263 39404748555664-bit doubleword at main memory address A– 8 –15-213, S’03Enhanced DRAMsEnhanced DRAMsAll enhanced DRAMs are built around the conventional All enhanced DRAMs are built around the conventional DRAM core. DRAM core. Fast page mode DRAM (FPM DRAM)Access contents of row with [RAS, CAS, CAS, CAS, CAS] instead of [(RAS,CAS), (RAS,CAS), (RAS,CAS), (RAS,CAS)].Extended data out DRAM (EDO DRAM)Enhanced FPM DRAM with more closely spaced CAS signals.Synchronous DRAM (SDRAM)Driven with rising clock edge instead of asynchronous control signals.Double data-rate synchronous DRAM (DDR SDRAM)Enhancement of SDRAM that uses both clock edges as control signals.Video RAM (VRAM)Like FPM DRAM, but output is produced by shifting row bufferDual ported (allows concurrent reads and writes)– 9 –15-213, S’03Nonvolatile MemoriesNonvolatile MemoriesDRAM and SRAM are volatile memoriesDRAM and SRAM are volatile memoriesLose information if powered off.Nonvolatile memories retain value even if powered off.Nonvolatile memories retain value even if powered off.Generic name is read-only memory (ROM).Misleading because some ROMs can be read and modified.Types of ROMsTypes of ROMsProgrammable ROM (PROM)Eraseable programmable ROM (EPROM)Electrically eraseable PROM (EEPROM)Flash memoryFirmwareFirmwareProgram stored in a ROMBoot time code, BIOS (basic input/ouput system)graphics cards, disk controllers.– 10 –15-213, S’03Typical Bus Structure Connecting CPU and MemoryTypical Bus Structure Connecting CPU and MemoryA A busbus is a collection of parallel wires that carry is a collection of parallel wires that carry address, data, and control signals.address, data, and control signals.Buses are typically shared by multiple devices.Buses are typically shared by multiple devices.mainmemoryI/O bridgebus interfaceALUregister fileCPU chipsystem bus memory bus– 11 –15-213, S’03Memory Read Transaction (1)Memory Read Transaction (1)CPU places address A on the memory bus.CPU places address A on the memory bus. ALUregister filebus interfaceA0Axmain memoryI/O bridge%eaxLoad operation: movl A, %eax– 12 –15-213, S’03Memory Read Transaction (2)Memory Read Transaction (2)Main memory reads A from the memory bus, retrieves Main memory reads A from the memory bus, retrieves word x, and places it on the bus.word x, and places it on the bus.ALUregister filebus interfacex0Axmain memory%eaxI/O bridgeLoad operation: movl A, %eax– 13 –15-213, S’03Memory Read Transaction (3)Memory Read Transaction (3)CPU read word x from the bus and copies it into CPU read word x from the bus and copies it into register %eax.register %eax.xALUregister filebus interfacexmain memory0A%eaxI/O bridgeLoad operation: movl A, %eax– 14 –15-213, S’03Memory Write Transaction (1)Memory Write Transaction (1) CPU places address A on bus. Main memory reads it CPU places address A on
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