Recitation #9, Section F, 15-213, Sp 06Virtual memorySlide 3Virtual and physical addressesPage Table translates VPN to PPNTranslation Lookaside Buffer (TLB)TLB and the L1-CacheWorst case? (most delay)?ExamplePart 1Example: TLB and page tablePart 2Slide 13Further material1Recitation #9, Section F, 15-213, Sp 06 Virtual memoryReminders:Quiz today: virtual memoryShell Lab due ThursdayTA: Jernej BarbicModified from: Kun Gao’s and Minglong Shao’s recitations, Spring 2005,Fall 20042Virtual memoryOne of the most important concepts in CSBenefits of virtual memory (VM):Use RAM as a cache for diskEasier memory managementSimplifies linking and loadingAccess protectionShare memory efficiently3Virtual memoryCPU0:1:N-1:Memory0:1:P-1:Page TableDiskVirtualAddressesPhysicalAddressesPage hit: page is in memoryPage fault: page is on diskPer Process:4Virtual and physical addressesvirtual page number (VPN) page offsetvirtual addressphysical page number (PPN)page offsetphysical address0p–1address translationpm–1n–10p–1pVirtual Memory: up to 2n -1 bytesPhysical Memory: up to 2m -1 bytes5Page Table translates VPN to PPNSeparate page table per each processVPN is the index into the page tablevirtual page number (VPN) page offsetvirtual addressphysical page number (PPN) page offsetphysical address0p–1pm–1n–1 0p–1ppage table base registerif valid=0then pagenot in memoryvalidphysical page number (PPN)accessVPN acts astable indexvirtual page number (VPN) page offsetvirtual addressphysical page number (PPN) page offsetphysical address0p–1pm–1n–1 0p–1ppage table base registerif valid=0then pagenot in memoryvalidphysical page number (PPN)accessVPN acts astable index6Translation Lookaside Buffer (TLB)Page table is in memory or even on disk(slow access)TLB keeps things manageableTLBCache/Memory1. VA 4. PAMMU/Translation2. VPN 3. PTE5. DataCPU7TLB and the L1-Cachevirtual addressvirtual page number page offsetphysical addressn–1 0p–1pvalid physical page numbertagvalid tag datadata=cache hittag byte offsetindex=TLB hitTLBL1-Cache...8Worst case? (most delay)?TLB miss, page fault on page table, then page fault on memory readTLBCache/Memory1. VA3. PTEA (PTBR + VPN)MMU/Translation2. VPN6. DataCPU4. PTE5. PADISKPage Fault/Page TablePage Fault/Mem Read9Example20-bit virtual addresses18-bit physical addressesPage size is 1024 bytesTLB is 2-way associative with 16 total entries10Part 1A. Virtual addressB. Physical address16 15 14 13 12 11 10 9 8 7 6 5 4 31718 2 1 019VPNVPOTLBT TLBI16 15 14 13 12 11 10 9 8 7 6 5 4 317 2 1 0PPNPPO11Example: TLB and page table12Part 2Virtual address 0x78E6A. 078E6 =B. Address translationC. Physical addressparameter Value Parameter ValueVPN 0x01E TLB hit? NTLB Index 0x6 Page fault? NTLB Tag 0x03 PPN 0x570000 0111 1000 1110 011001 0101 1100 1110 011013Part 2Virtual address 0x04AA4A. 04AA4 = 0000 0100 1010 1010 0100B. Address translationC. Physical address 01 1010 0010 1010 0100parameter Value Parameter ValueVPN 0x012 TLB hit? YTLB Index 0x2 Page fault? NTLB Tag 0x02 PPN 0x6814Further materialSection 10.6.4: a concrete exampleRead carefully and solve practice problem
View Full Document
Unlocking...