Memory Technology March 14, 2000Computer SystemLevels in Memory HierarchyScaling to 0.1µmStatic RAM (SRAM)Anatomy of an SRAM CellSRAM Cell PrincipleBistable ElementExample SRAM Configuration (16 x 8)Dynamic RAM (DRAM)Anatomy of a DRAM CellAddressing Arrays with BitsExample 2-Level Decode DRAM (64Kx1)DRAM OperationObservations About DRAMsEnhanced Performance DRAMsVideo RAMDRAM Driving ForcesDRAM Storage CapacitorTrench CapacitorIBM DRAM EvolutionMitsubishi Stacked Cell DRAMMitsubishi DRAM PicturesMagnetic DisksDisk CapacityDisk OperationDisk PerformanceDisk / System InterfaceMagnetic Disk TechnologyCD Read Only Memory (CDROM)Storage TrendsStorage Price: $/MByteStorage Access Times (nsec)Processor clock ratesThe CPU vs. DRAM Latency Gap (ns)Memory Technology SummaryTopics•Memory Hierarchy Basics•Static RAM•Dynamic RAM•Magnetic Disks•Access Time Gapclass17.ppt15-213Memory TechnologyMarch 14, 2000CS 213 S’00– 2 –class17.pptComputer SystemDiskDiskMemory-I/O busMemory-I/O busProcessorProcessorCacheCacheMemoryMemoryI/OcontrollerI/OcontrollerI/OcontrollerI/OcontrollerI/OcontrollerI/OcontrollerDisplayDisplayNetworkNetworkRegCS 213 S’00– 3 –class17.pptLevels in Memory HierarchyCPUCPUregsregsCacheMemoryMemorydiskdisksize:speed:$/Mbyte:block size:200 B2 ns8 BRegister Cache Memory Disk Memory32KB - 4MB4 ns$100/MB32 B128 MB60 ns$1.50/MB8 KB20 GB8 ms$0.05/MBlarger, slower, cheaper8 B 32 B 8 KBcache virtual memoryCS 213 S’00– 4 –class17.pptScaling to 0.1µm•Semiconductor Industry Association, 1992 Technology Workshop–Projected future technology based on past trends1992 1995 1998 2001 2004 2007Feature size: 0.5 0.35 0.25 0.18 0.12 0.10–Industry is slightly ahead of projectionDRAM capacity: 16M 64M 256M 1G 4G 16G–Doubles every 1.5 years–Prediction on trackChip area (cm2): 2.5 4.0 6.0 8.0 10.012.5–Way off! Chips staying smallCS 213 S’00– 5 –class17.pptStatic RAM (SRAM)Fast•~4 nsec access timePersistent •as long as power is supplied•no refresh required Expensive •~$100/MByte•6 transistors/bitStable•High immunity to noise and environmental disturbancesTechnology for cachesCS 213 S’00– 6 –class17.pptAnatomy of an SRAM Cell(6 transistors)bb’bit linebit lineword lineRead:1. set bit lines high2. set word line high3. see which bit line goes lowWrite:1. set bit lines to new data value•b’ is set to the opposite of b2. raise word line to “high” sets cell to new state (may involve flipping relative to old state)0 1Stable Configurations1 0Terminology:bit line: carries dataword line: used for addressingCS 213 S’00– 7 –class17.pptSRAM Cell PrincipleInverter Amplifies•Negative gain•Slope < –1 in middle•Saturates at endsInverter Pair Amplifies•Positive gain•Slope > 1 in middle•Saturates at endsVinV1V2V1V2Vin0 0.2 0.4 0.6 0.8 100.10.20.30.40.50.60.70.80.91CS 213 S’00– 8 –class17.pptBistable ElementStability•Require Vin = V2•Stable at endpoints–recover from pertubation•Metastable in middle–Fall out when perturbedBall on Ramp AnalogyVinV1V2VinV2Vin0 0.2 0.4 0.6 0.8 100.10.20.30.40.50.60.70.80.91StableMetastableStable0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1CS 213 S’00– 9 –class17.pptsense/writeampssense/writeampsExample SRAM Configuration (16 x 8)AddressdecoderAddressdecoderA0A1A2A3b7’b7d7sense/writeampssense/writeampsb1’b1d1sense/writeampssense/writeampsb0’b0d0Input/output linesW0W1W15memorycellsR/WCS 213 S’00– 10 –class17.pptDynamic RAM (DRAM)Slower than SRAM •access time ~60 nsecNonpersistant •every row must be accessed every ~1 ms (refreshed)Cheaper than SRAM •~$1.50 / MByte•1 transistor/bitFragile•electrical noise, light, radiationWorkhorse memory technologyCS 213 S’00– 11 –class17.pptAnatomy of a DRAM CellWord LineBitLineStorage NodeAccessTransistorCnodeCBLWritingWord LineBit LineReadingWord LineBit LineV ~ Cnode / CBLVStorage NodeCS 213 S’00– 12 –class17.pptrowaddress =col0 1 2 30 000 001 010 0111 100 101 110 111row 1col 2Addressing Arrays with Bitsr cnArray Size•R rows, R = 2r•C columns, C = 2c•N = R * C bits of memoryAddressing•Addresses are n bits, where N = 2n•row(address) = address / C –leftmost r bits of address•col(address) = address % C –rightmost bits of addressExample•R = 2•C = 4•address = 6CS 213 S’00– 13 –class17.pptExample 2-Level Decode DRAM (64Kx1)RowaddresslatchRowaddresslatchColumnaddresslatchColumnaddresslatchRow decoderRow decoder256x256cell array256x256cell arraycolumnlatch and decodercolumnlatch and decoderA7-A0\8\8R/W’DoutDinCASRASrowcol256 Rows256 Columnscolumnsense/writeampscolumnsense/writeampsProvide 16-bit address in two 8-bit chunksCS 213 S’00– 14 –class17.pptDRAM OperationRow Address (~50ns)•Set Row address on address lines & strobe RAS•Entire row read & stored in column latches•Contents of row of memory cells destroyedColumn Address (~10ns)•Set Column address on address lines & strobe CAS•Access selected bit–READ: transfer from selected column latch to Dout–WRITE: Set selected column latch to DinRewrite (~30ns)•Write back entire rowCS 213 S’00– 15 –class17.pptObservations About DRAMsTiming•Access time (= 60ns) < cycle time (= 90ns)•Need to rewrite rowMust Refresh Periodically•Perform complete memory cycle for each row•Approximately once every 1ms•Sqrt(n) cycles•Handled in background by memory controllerInefficient Way to Get a Single Bit•Effectively read entire row of Sqrt(n) bitsCS 213 S’00– 16 –class17.pptEnhanced Performance DRAMsRowaddresslatchRowaddresslatchColumnaddresslatchColumnaddresslatchRow decoderRow decoder256x256cell array256x256cell arraysense/writeampssense/writeampscolumnlatch and decodercolumnlatch and decoderA7-A0\8\8R/W’CASRASrowcolEntire row buffered hererow access time col access time cycle time page mode cycle time 50ns 10ns 90ns 25nsConventional Access•Row + Col•RAS CAS RAS CAS ...Page Mode•Row + Series of columns•RAS CAS CAS CAS ...•Gives successive bitsOther Acronyms•EDORAM–“Extended data output”•SDRAM–“Synchronous DRAM”Typical PerformanceCS 213 S’00– 17 –class17.pptPerformance Enhanced for Video / Graphics Operations•Frame buffer to hold graphics imageWriting•Random access of bits•Also supports rectangle fill operations–Set all bits in region to 0 or 1Reading•Load entire row into shift register•Shift out at video
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