Memory SystemCase StudiesMar. 20, 2008TopicsP6 address translationx86-64 extensionsLinux memory managementLinux page fault handlingMemory mappingclass17.ppt15-213“The course that gives CMU its Zip!”215-213, S’08Intel P6(Bob Colwell’s Chip, CMU Alumni)Internal designation for successor to PentiumWhich had internal designation P5Fundamentally different from PentiumOut-of-order, superscalar operationResulting processorsPentium Pro (1996)Pentium II (1997)L2 cache on same chipPentium III (1999)The freshwater fish machinesSaltwater fish machines: Pentium 4Saltwater fish machines: Pentium 4Different operation, but similar memory systemAbandoned by Intel in 2005 for P6-based Core 2 Duo315-213, S’08P6 Memory Systembus interface unitDRAMexternal system bus (e.g. PCI)instruction fetch unitL1i-cacheL2cachecache busL1d-cacheinstTLBdataTLBprocessor package 32 bit address space 4 KB page size L1, L2, and TLBs 4-way set associative Inst TLB 32 entries 8 sets Data TLB 64 entries 16 sets L1 i-cache and d-cache 16 KB 32 B line size 128 sets L2 cache unified 128 KB -- 2 MB415-213, S’08Review of AbbreviationsSymbols:Components of the virtual address (VA)TLBI: TLB indexTLBT: TLB tagVPO: virtual page offset VPN: virtual page number Components of the physical address (PA)PPO: physical page offset (same as VPO)PPN: physical page numberCO: byte offset within cache lineCI: cache indexCT: cache tag515-213, S’08Overview of P6 Address TranslationCPUVPN VPO20 12TLBT TLBI416virtual address (VA)...TLB (16 sets, 4 entries/set)VPN1 VPN21010PDE PTEPDBRPPN PPO20 12Page tablesTLBmissTLBhitphysicaladdress (PA)result32...CT CO20 5CI7L2 and DRAML1 (128 sets, 4 lines/set)L1hitL1miss615-213, S’08P6 2-level Page Table StructurePage directory 1024 4-byte page directory entries (PDEs) that point to page tablesOne page directory per process.Page directory must be in memory when its process is runningAlways pointed to by PDBRPage tables:1024 4-byte page table entries (PTEs) that point to pages.Page tables can be paged in and out.page directory...Up to 1024 page tables1024PTEs1024PTEs1024PTEs...1024PDEs715-213, S’08P6 Page Directory Entry (PDE)Page table physical base addr Avail G PS A CD WT U/S R/W P=1Page table physical base address: 20 most significant bits of physical page table address (forces page tables to be 4KB aligned)Avail: These bits available for system programmersG: global page (don’t evict from TLB on task switch)PS: page size 4K (0) or 4M (1)A: accessed (set by MMU on reads and writes, cleared by software) CD: cache disabled (1) or enabled (0)WT: write-through or write-back cache policy for this page tableU/S: user or supervisor mode accessR/W: read-only or read-write accessP: page table is present in memory (1) or not (0)31 12 11 9 8 7 6 5 4 3 2 1 0Available for OS (page table location in secondary storage) P=031 01815-213, S’08P6 Page Table Entry (PTE)Page physical base address Avail G 0 D A CD WT U/S R/W P=1Page base address: 20 most significant bits of physical page address (forces pages to be 4 KB aligned)Avail: available for system programmersG: global page (don’t evict from TLB on task switch)D: dirty (set by MMU on writes)A: accessed (set by MMU on reads and writes) CD: cache disabled or enabledWT: write-through or write-back cache policy for this pageU/S: user/supervisorR/W: read/writeP: page is present in physical memory (1) or not (0)31 12 11 9 8 7 6 5 4 3 2 1 0Available for OS (page location in secondary storage) P=031 01915-213, S’08How P6 Page Tables Map VirtualAddresses to Physical OnesPDEPDBRphysical addressof page table base(if P=1)physical addressof page base(if P=1)physical addressof page directoryword offset into page directoryword offset into page tablepage directory page tableVPN110VPO10 12VPN2Virtual addressPTEPPN PPO2012Physical addressword offset into physical and virtualpage1015-213, S’08Representation of VM Address SpaceSimplified Example16 page virtual address spaceFlagsP: Is entry in physical memory?M: Has this part of VA space been mapped?Page DirectoryPT 3P=1, M=1P=1, M=1P=0, M=0P=0, M=1••••P=1, M=1P=0, M=0P=1, M=1P=0, M=1••••P=1, M=1P=0, M=0P=1, M=1P=0, M=1••••P=0, M=1P=0, M=1P=0, M=0P=0, M=0••••PT 2PT 0Page 0Page 1Page 2Page 3Page 4Page 5Page 6Page 7Page 8Page 9Page 10Page 11Page 12Page 13Page 14Page 15Mem AddrDisk AddrIn MemOn DiskUnmapped1215-213, S’08P6 TLBTLB entry (not all documented, so this is speculative):V: indicates a valid (1) or invalid (0) TLB entryTag: disambiguates entries cached in the same setPPN: translation of the address indicated by index & tagG: page is “global” according to PDE, PTES: page is “supervisor-only” according to PDE, PTEW: page is writable according to PDE, PTED: PTE has already been marked “dirty” (once is enough)Structure of the data TLB:16 sets, 4 entries/setPPN Tag W11620S1G1V1D1entry entry entry entryentry entry entry entryentry entry entry entry...set 0set 1set 151315-213, S’08Translating with the P6 TLB1. Partition VPN into TLBT and TLBI.2. Is the PTE for VPN cached in set TLBI?3. 3. YesYes: then check : then check permissions, build permissions, build physical address. physical address. 4. No: then read PTE (and PDE if not cached) from memory and build physical address.CPUVPN VPO20 12TLBT TLBI416virtual addressPDE PTE...TLBmissTLBhitpage table translationPPN PPO20 12physical address12341515-213, S’08Translating with the P6 Page Tables(case 1/1) Case 1/1: page table and page present.MMU Action: MMU builds physical address and fetches data word.OS actionNoneVPNVPN1 VPN2PDEPDBRPPN PPO20 1220VPO12p=1 PTE p=1Data pagedataPage directoryPage tableMemDisk1615-213, S’08Translating with the P6 Page Tables(case 1/0)Case 1/0: page table present but page missing.MMU Action: Page fault exceptionHandler receives the following args:%EIP that caused faultVA that caused faultFault caused by non-present page or page-level protection violationRead/writeUser/supervisorVPNVPN1 VPN2PDEPDBR20VPO12p=1 PTEPage directoryPage tableMemDiskData pagedatap=01715-213, S’08Translating with the P6 Page Tables(case 1/0, cont)OS Action: Check for a legal virtual address.Read PTE through PDE. Find free physical page (swapping out current page if necessary)Read virtual page from disk into physical pageAdjust PTE to point to
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