Memory System Case Studies Oct. 27, 2006Intel P6 (Bob Colwell’s Chip, CMU Alumni)P6 Memory SystemReview of AbbreviationsOverview of P6 Address TranslationP6 2-level Page Table StructureP6 Page Directory Entry (PDE)P6 Page Table Entry (PTE)How P6 Page Tables Map Virtual Addresses to Physical OnesRepresentation of VM Address SpaceP6 TLB TranslationP6 TLBTranslating with the P6 TLBP6 Page Table TranslationTranslating with the P6 Page Tables (case 1/1)Translating with the P6 Page Tables (case 1/0)Translating with the P6 Page Tables (case 1/0, cont)Translating with the P6 Page Tables (case 0/1)Translating with the P6 Page Tables (case 0/0)Translating with the P6 Page Tables (case 0/0, cont)P6 L1 Cache AccessL1 Cache AccessSpeeding Up L1 Accessx86-64 PagingSlide 25Linux Organizes VM as Collection of “Areas”Linux Page Fault HandlingMemory MappingUser-Level Memory Mappingmmap() Example: Fast File CopyExec() RevisitedFork() RevisitedMemory System SummaryMemory SystemCase StudiesOct. 27, 2006Memory SystemCase StudiesOct. 27, 2006TopicsP6 address translationx86-64 extensionsLinux memory managementLinux page fault handlingMemory mappingclass17.ppt15-213“The course that gives CMU its Zip!”– 2 –15-213, F’06Intel P6(Bob Colwell’s Chip, CMU Alumni)Internal designation for successor to PentiumWhich had internal designation P5Fundamentally different from PentiumOut-of-order, superscalar operationResulting processorsPentium Pro (1996)Pentium II (1997)L2 cache on same chipPentium III (1999)The freshwater fish machinesSaltwater fish machines: Pentium 4Saltwater fish machines: Pentium 4Different operation, but similar memory systemAbandoned by Intel in 2005 for P6 based Core 2 Duo– 3 –15-213, F’06P6 Memory SystemP6 Memory Systembus interface unitDRAMexternal system bus (e.g. PCI)instruction fetch unitL1i-cacheL2cachecache busL1d-cacheinstTLBdataTLBprocessor package 32 bit address space 4 KB page size L1, L2, and TLBs 4-way set associative Inst TLB 32 entries 8 sets Data TLB 64 entries 16 sets L1 i-cache and d-cache 16 KB 32 B line size 128 sets L2 cache unified 128 KB -- 2 MB– 4 –15-213, F’06Review of AbbreviationsReview of AbbreviationsSymbols:Components of the virtual address (VA)TLBI: TLB indexTLBT: TLB tagVPO: virtual page offset VPN: virtual page number Components of the physical address (PA)PPO: physical page offset (same as VPO)PPN: physical page numberCO: byte offset within cache lineCI: cache indexCT: cache tag– 5 –15-213, F’06Overview of P6 Address TranslationOverview of P6 Address TranslationCPUVPN VPO20 12TLBT TLBI416virtual address (VA)...TLB (16 sets, 4 entries/set)VPN1 VPN21010PDE PTEPDBRPPN PPO20 12Page tablesTLBmissTLBhitphysicaladdress (PA)result32...CT CO20 5CI7L2 and DRAML1 (128 sets, 4 lines/set)L1hitL1miss– 6 –15-213, F’06P6 2-level Page Table StructureP6 2-level Page Table StructurePage directory 1024 4-byte page directory entries (PDEs) that point to page tablesOne page directory per process.Page directory must be in memory when its process is runningAlways pointed to by PDBRPage tables:1024 4-byte page table entries (PTEs) that point to pages.Page tables can be paged in and out.page directory...Up to 1024 page tables1024PTEs1024PTEs1024PTEs...1024PDEs– 7 –15-213, F’06P6 Page Directory Entry (PDE)P6 Page Directory Entry (PDE)Page table physical base addr Avail G PS A CD WT U/S R/W P=1Page table physical base address: 20 most significant bits of physical page table address (forces page tables to be 4KB aligned)Avail: These bits available for system programmersG: global page (don’t evict from TLB on task switch)PS: page size 4K (0) or 4M (1)A: accessed (set by MMU on reads and writes, cleared by software) CD: cache disabled (1) or enabled (0)WT: write-through or write-back cache policy for this page tableU/S: user or supervisor mode accessR/W: read-only or read-write accessP: page table is present in memory (1) or not (0)31 12 11 9 8 7 6 5 4 3 2 1 0Available for OS (page table location in secondary storage) P=031 01– 8 –15-213, F’06P6 Page Table Entry (PTE)P6 Page Table Entry (PTE)Page physical base address Avail G 0 D A CD WT U/S R/W P=1Page base address: 20 most significant bits of physical page address (forces pages to be 4 KB aligned)Avail: available for system programmersG: global page (don’t evict from TLB on task switch)D: dirty (set by MMU on writes)A: accessed (set by MMU on reads and writes) CD: cache disabled or enabledWT: write-through or write-back cache policy for this pageU/S: user/supervisorR/W: read/writeP: page is present in physical memory (1) or not (0)31 12 11 9 8 7 6 5 4 3 2 1 0Available for OS (page location in secondary storage) P=031 01– 9 –15-213, F’06How P6 Page Tables Map VirtualAddresses to Physical OnesHow P6 Page Tables Map VirtualAddresses to Physical OnesPDEPDBRphysical addressof page table base(if P=1)physical addressof page base(if P=1)physical addressof page directoryword offset into page directoryword offset into page tablepage directory page tableVPN110VPO10 12VPN2Virtual addressPTEPPN PPO2012Physical addressword offset into physical and virtualpage– 10 –15-213, F’06Representation of VM Address SpaceRepresentation of VM Address SpaceSimplified Example16 page virtual address spaceFlagsP: Is entry in physical memory?M: Has this part of VA space been mapped?Page DirectoryPT 3P=1, M=1P=1, M=1P=0, M=0P=0, M=1••••P=1, M=1P=0, M=0P=1, M=1P=0, M=1••••P=1, M=1P=0, M=0P=1, M=1P=0, M=1••••P=0, M=1P=0, M=1P=0, M=0P=0, M=0••••PT 2PT 0Page 0Page 1Page 2Page 3Page 4Page 5Page 6Page 7Page 8Page 9Page 10Page 11Page 12Page 13Page 14Page 15Mem AddrDisk AddrIn MemOn DiskUnmapped– 11 –15-213, F’06P6 TLB TranslationP6 TLB TranslationCPUVPN VPO20 12TLBT TLBI416virtual address (VA)...TLB (16 sets, 4 entries/set)VPN1 VPN21010PDE PTEPDBRPPN PPO20 12Page tablesTLBmissTLBhitphysicaladdress (PA)result32...CT CO20 5CI7L2 and DRAML1 (128 sets, 4 lines/set)L1hitL1miss– 12 –15-213, F’06P6 TLBP6 TLBTLB entry (not all documented, so this is speculative):V: indicates a valid (1) or invalid (0) TLB entryPD: is this entry a PDE (1) or a PTE (0)?tag: disambiguates entries cached in the same setPDE/PTE: page directory or page table entryStructure of the data TLB:16 sets, 4 entries/setPDE/PTE Tag PD V1 11632entry
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